Hipólito Guzmán-Miranda

Noninvasive Fault Classification, Robustness and Recovery Time Measurement in Microprocessor-Type Architectures Subjected to Radiation-Induced Errors

In critical digital designs such as aerospace or safety equipment, radiation-induced upset events (single-event effects or SEEs) can produce adverse effects, and therefore, the ability to compare the sensitivity of various proposed solutions is desirable. As custom-hardened microprocessor solutions can be very costly, the reliability of various commercial off-the-shelf (COTS) processors can be evaluated to see if there is a commercially available microprocessor or microprocessor-type intellectual property (IP) with adequate robustness for the specific application. Most existing approaches for the measurement of this robustness of the microprocessor involve diverting the program flow and timing to introduce the bit flips via interrupts and embedded handlers added to the application program. In this paper, a tool based on an emulation platform using Xilinx field programmable gate arrays (FPGAs) is described, which provides an environment and methodology for the evaluation of the sensitivity of microprocessor architectures, using dynamic runtime fault injection. A case study is presented, where the robustness of MicroBlaze and Leon3 microprocessors executing a simple signal processing task written in C language is evaluated and compared. A hardened version of the program, where the key variables are protected, has also been tested, and its contributions to system robustness have also been evaluated. In addition, this paper presents a further improvement in the developed tool that allows not only the measurement of microprocessor robustness but, in addition, the study and classification of single-event upset (SEU) effects and the exact measurement of the recovery time (the time that the microprocessor takes to self repair and recover the fault-free state). The measurement of this recovery time is important for real-time critical applications, where criticality depends on both data correctness and timing. To demonstrate the proposed improvements, a new software program that implements two different software hardening techniques (one for Data and another for Control Flow) has been made, and a study of the recovery times in some significant fault-injection cases has been performed over the Leon3 processor.

A Novel Co-Design Approach for Soft Errors Mitigation in Embedded Systems

There is an increasing concern about the mitigation of radiation effects in embedded systems. This fact is demanding new flexible design methodologies and tools that allow dealing with design constraints and dependability requirements at the same time. This paper presents a novel proposal to design radiation-tolerant embedded systems combining hardware and software mitigation techniques. A hardening infrastructure, which facilitates the design space exploration and the trade-offs analyses, has been developed to support this fault tolerance co-design approach. The advantages of our proposal are illustrated by means of a case study.

Compiler-Directed Soft Error Mitigation for Embedded Systems

The protection of processor-based systems to mitigate the harmful effect of transient faults (soft errors) is gaining importance as technology shrinks. At the same time, for large segments of embedded markets, parameters like cost and performance continue to be as important as reliability. This paper presents a compiler-based methodology for facilitating the design of fault-tolerant embedded systems. The methodology is supported by an infrastructure that permits to easily combine hardware/software soft errors mitigation techniques in order to best satisfy both usual design constraints and dependability requirements. It is based on a generic microprocessor architecture that facilitates the implementation of software-based techniques, providing a uniform isolated-from-target hardening core that allows the automatic generation of protected source code (hardened code). Two case studies are presented. In the first one, several software-based mitigation techniques are implemented and evaluated showing the flexibility of the infrastructure. In the second one, a customized fault tolerant embedded system is designed by combining selective protection on both hardware and software. Several trade-offs among performance, code size, reliability, and hardware costs have been explored. Results show the applicability of the approach. Among the developed software-based mitigation techniques, a novel selective version of the well known SWIFT-R is presented.

Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs

Today, many companies are facing the problem of component obsolescence in embedded systems. The incredibly fast growth rate of semiconductor companies is reducing dramatically the time components are available on the market. Twenty years ago, components remained on the market for 5 to 10 years; nowadays, they disappear from the market in less than two years. Developers of safety- or mission-critical systems are particularly sensitive to the obsolescence problem as their systems are expected to remain operative for very long periods (e.g., 30 years or more), and maintaining them fully operative is becoming difficult as the needed components may no longer be available. A possible solution for this problem may be the implementation of the needed components using FPGAs. The purpose of this paper is to provide an overview of the different possibilities designers have to face when developing such dependability-oriented solution. Also, a design flow is presented, describing its applicability to the implementation of processor cores, to be employed as a replacement of obsolete parts in safety- or mission-critical applications. Results show that there is a strong dependence of the reliability of the design with the specific application. The scrubbing process can also be optimized using the related technique.

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications

Mission-critical applications such as space or avionics increasingly demand high fault tolerance capabilities of their electronic systems. Among the fault tolerance characteristics, the performance and costs of an electronic system remain the leader factors in the space and avionics market. In particular, when considering SRAM-based FPGAs, specific hardening techniques generally based on Triple Modular Redundancy need to be adopted in order to guarantee the desired fault tolerance degree. While effectively increasing the fault tolerance capability, these techniques introduce an important performance degradation and a dramatic area overhead, that results in higher design costs. In this paper, we propose an innovative design flow that allow the implementation of fault tolerance circuits in SRAM-based FPGA devices with different fault tolerance capability degrees. We introduce a new metric that allows a designer to precisely estimate and set the desired fault tolerance capabilities. Experimental analysis performed on a realistic industrial-type case study demonstrates the efficiency of our methodology.

FT-UNSHADES-uP: A platform for the analysis and optimal hardening of embedded systems in radiation environments

Designing dependable systems is a systematic task where area, power and performance are competing constraints. In many applications, design restrictions do not permit the total hardening of a design, leaving some internal circuitry vulnerable to radiation effects. Hierarchical analysis is necessary to identify the relative importance and vulnerability of individual sub-circuits in a design so that selective hardening can be optimally applied. This paper describes the tool FT-UNSHADES-uP which provides an environment and methodology for the rapid dynamic hierarchical analysis of embedded based processor systems using runtime fault injection. A case study is presented, analyzing the effects of fault injection in the embedded RAM and internal registers of a MicroBlaze uP system. The results can be used for the optimal hardening of the FPGA or ASIC design.

FTUNSHADES2: A novel platform for early evaluation of robustness against SEE

Large digital integrated circuits designed to solve space applications, have to be designed following standards that recommend to include hardening techniques against Single Event Phenomena caused by harsh radiation environments. It is specifically important in the case of modern deep-submicron technologies. Single Event Effects are phenomena related to the effects of radiation when ionizing particles hit the surface of semiconductors in certain critical areas, where the consequences are mainly data corruption or unexpected behavior with no permanent damage. Fault injection studies are a valuable methodology to evaluate the robustness of the circuit mainly in the early stages of the design. This paper introduces the second generation of the emulation-based fault injection platform FTUNSHADES supported by the European Space Agency, where new features have been included to fulfill with the demands of a growing community of users.

Pulsed Laser SEU Cross Section Measurement Using Coincidence Detectors

This work presents the determination of a Pulsed Laser SEU Cross-Section (Count Statistics). In this work, a coincidence detector has been used to count fault events by comparing the digital VLSI circuit under test with a replica of the design running on a control FPGA. A SEU is declared when a specific fault pattern is detected. The target chip design generates specific fault patterns under pulsed laser shinning. Sweeping the laser energy on a flip flop of a Shift Register, data for a cross section analysis it is obtained. The coincidence detector was previously tested in a preliminary radiation test, so all the lessons learned in the design of radiation test can be translated for future works. In this work it has been used the pulsed laser facilities of Spanish National Laser Center in Salamanca.

Exploiting Fault Model Correlations to Accelerate SEU Sensitivity Assessment

Nowadays, integrated circuit technologies are increasingly being more susceptible to ionizing radiation effects. In order to assess the reliability of a digital system performing a specific application and to identify the most critical failure effects, radiation experiments and fault injection campaigns are usually performed, which may be costly and time-expensive. This paper proposes a fully automated, practical methodology for accelerating Single-Event-Upset (SEU) fault injection campaigns in digital circuits. The main underlying principle is based on the correlation between the effects of the SEU fault model with the Stuck-At (SA) one. Circuital and functional analysis and experimental case studies confirm the effectiveness of the proposed solutions.

Soft core based embedded systems in critical aerospace applications

There is an increasing interest in the aerospace industry to reduce the cost of the systems by means of using Commercial Off The Shelf (COTS) devices. The engineering of novel microsatellites and nanosatellites are clear examples of this new trend. However, the use of sub-micron technologies has led to greater sensitivity of these devices to radiation-induced transient faults, limiting the exploitation of this approach in critical systems. This paper presents an innovative application of soft-core microprocessor based embedded systems, to design dependable and reduced-cost critical systems with COTS reconfigurable devices (flash based FPGAs). To make this possible, it is necessary to fine-tune the protection strategy by combining selectively fault mitigation techniques based on hardware or software. In this way, the resultant system not only fulfills both the design constraints and the dependability requirements, but also avoids the cost provoked by excessive use of protection mechanisms. A case study is presented in which the design space exploration between hardware and software protection techniques permits to find the best trade-offs among performance, reliability, memory size and hardware cost in a dependable subsystem.