A.P. Vega-Leal

A Test of HIL COTS Technology for Fuel Cell Systems Emulation

The objective of this paper is twofold: a simple formal test to verify that an emulator hardware-in-the-loop (HIL) technology is well suited for specific purposes (the HIL test) and the implementation of an HIL system using very common commercial-off-the-shelf technology (Peripheral component interconnect eXtensions for instrumentation modular instrumentation, LabVIEW Real Time, and Simulink Software Platforms). The HIL approach is used to develop electronic controllers for fuel cell systems (FCSs) by emulation of the FCS. As a conclusion, the HIL test in that specific application is assessed.

Pulsed Laser SEU Cross Section Measurement Using Coincidence Detectors

This work presents the determination of a Pulsed Laser SEU Cross-Section (Count Statistics). In this work, a coincidence detector has been used to count fault events by comparing the digital VLSI circuit under test with a replica of the design running on a control FPGA. A SEU is declared when a specific fault pattern is detected. The target chip design generates specific fault patterns under pulsed laser shinning. Sweeping the laser energy on a flip flop of a Shift Register, data for a cross section analysis it is obtained. The coincidence detector was previously tested in a preliminary radiation test, so all the lessons learned in the design of radiation test can be translated for future works. In this work it has been used the pulsed laser facilities of Spanish National Laser Center in Salamanca.

A Complete Emulation System for Single Event Effects Analysis

Trends show that next coming technologies will produce new generations of very large circuits, running at high clock rates. Some critical applications will have to be protected against the remaining radiation at sea level. This is especially important in aerospace applications because ionizing radiation produces corruption of the internal state. New design methods have to be introduced to assure circuits will tolerate the impact of single event effects (SEE). It is very important to be able to analyze which parts of the circuits are more critical and how the behavior of the global system is degraded when one part suffers a SEE. This paper presents the last functionalities added to the FT-UNSHADES system to extend the analysis to SETs and MBUs. As a result, the system can insert and analyze many fault types at a rate of 180 K faults per hour in a system with 2 million test vectors.

New multirate bandpass sigma-delta modulators

A new architecture for fourth- and sixth-order bandpass sigma-delta (BP-SD) modulators is proposed here. The basic BP-SD modulator is obtained from its low-pass (LP) counterpart by means of the standard transformation z/sup -1/ /spl rarr/ -z/sup -2/, which transforms the integrators in the LP modulator into resonators in the BP modulator, and places the input signal band at the frequency f/sub s//4, where f/sub s/ is the sampling rate. In the proposed architecture, the second resonator (and the third one for the sixth-order case) is implemented using a two-path strategy, by means of two high-pass filters (whose poles are located at f/sub s//2) operating in a time-interleaved mode. However, unlike other BP-SD modulators using the two-path strategy, in our approach, the effective sampling frequency in the second resonator (and in the third one for the sixth-order case) is increased to 2/spl middot/f/sub s/ by maintaining the clock rate of the high-pass filters to f/sub s/ which, in turn, places their poles at f/sub s//2. The signal band in the input of the second resonator is moved from the center frequency f/sub s//4 to f/sub s//2 by a modulation process that separates the signal into their in-phase and quadrature components. Another demodulation process in the digital domain reverses this frequency translation of the signal band before the output signal is converted to the analog domain and fed back to the modulator input. A detailed theoretical analysis of the architecture is done in the paper. Owing to the multirate nature of the proposed modulators, simulation results show an improvement of approximately 12 dB in the input dynamic range (fourth-order case) when compared to conventional modulators of the same order clocked at the same frequency rate (in the first resonator).

Multirate-multibit sigma-delta modulators

A multirate architecture for implementation of SD modulator is proposed in this paper. The performance of the called MM (multirate-multibit) SD modulator is the same that a conventional multibit SD modulator working at the clock rate of the first integrator, but the ADC in the forward path is replaced by an increase at the clock rate of the second integrator. Theoretical and simulation results are presented.

The experience of starting-up a radiation test at the 18MeV cyclotron in the Spanish National Accelerators Center

Space application integrated circuits have large and complex validation process. One of the most expensive stage is the radiation test. There are few facilities qualified to satisfy the requirements of standards. Low power accelerators are used to simplify the validation process, because they usually have beam time, lower costs, and flexibility to access. As prevalidation tools they can provide valuable information about the circuit behavior. In this paper the first experience of irradiation to a silicon device during its execution in the Spanish National Accelerator Center is described. A radiation test using a semi-custom programmable (CPLD) commercial technology has been set-up. During this experience the CPLD has been irradiated with protons at 18 MeV while the device was running with a custom design. Results obtained are described and the damage over the device has been understood as total ionization dose.

A 1.1 V very low-power /spl Sigma//spl Delta/ modulator for 14-b 16 kHz A/D conversion using a novel class AB transconductance amplifier

This paper presents a second order /spl Sigma//spl Delta/ modulator implementation for a supply voltage of 1.1 V. A new fully differential CMOS class AB transconductance amplifier has been designed in order to achieve high-resolution under very-low-voltage and very-low-power operation. The modulator has been implemented using the AMS/spl I.bar/CDS 0.35 /spl mu/m CMOS technology and postlayout simulations have been performed showing 14 bits of resolution with an oversampling ratio of 160 and less than 40 /spl mu/W of quiescent power consumption. To the authors knowledge no other /spl Sigma//spl Delta/ modulator has been reported with such a low quiescent consumption that achieves similar dynamic range and signal bandwidth.

A 1.1 V low-power /spl Sigma//spl Delta/ modulator for 14-b 16 kHz A/D conversion

This paper presents a second order /spl Sigma//spl Delta/ modulator implementation for a supply voltage of 1.1 V. A new fully-differential CMOS operational amplifier has been designed in order to achieve high-resolution under very-low-voltage operation. The design relies on the elimination of critical switches by using a voltage doubler. The modulator has been implemented using the AMS CDS 0.35 /spl mu/m CMOS technology and postlayout simulations have been performed. These simulations showed 14 bits of resolution with an oversampling ratio of 166.

Open System Architecture for GERD pH and Impedance Measurement

In the last years, companies which provide consumables and medical devices have developed several catheter designs to study Gastroesophageal Reflux Disease (GERD). If research groups want to incorporate the information from this catheter together with more biological parameters for their studies, open systems must be developed, allowing the integration of different probes with general purpose digital acquisition systems. This paper presents the comparison of the results of proposed probes in literature, focus on innovative solutions more suitable for medical applications.

Stochastic Resonance as a null distortion demodulation

We present an analogy between FM modulation and stochastic resonance and a stochastic resonance (SR) condition from that analysis. The SR is possible when there is no signal harmonic distortion at the FM demodulator output. The non-THD condition is experimentally demonstrated with an ad-hoc test bench and an algorithm, implemented as a virtual instrument, for SR tuning is also shown. A THD characterization of stochastic resonance let to use digital filtering for tuning the optimal noise level.