J. Napoles

Selective Harmonic Mitigation Technique for High-Power Converters

In high-power applications, the maximum switching frequency is limited due to thermal losses. This leads to highly distorted output waveforms. In such applications, it is necessary to filter the output waveforms using bulky passive filtering systems. The recently presented selective harmonic mitigation pulsewidth modulation (SHMPWM) technique produces output waveforms where the harmonic distortion is limited, fulfilling specific grid codes when the number of switching angles is high enough. The related technique has been previously presented using a switching frequency that is equal to 750 Hz. In this paper, a special implementation of the SHMPWM technique optimized for very low switching frequency is studied. Experimental results obtained applying SHMPWM to a three-level neutral-point-clamped converter using a switching frequency that is equal to 350 Hz are presented. The obtained results show that the SHMPWM technique improves the results of previous selective harmonic elimination pulsewidth modulation techniques for very low switching frequencies. This fact highlights that the SHMPWM technique is very useful in high-power applications, leading its use to an important reduction of the bulky and expensive filtering elements.

Selective Harmonic Mitigation Technique for Cascaded H-Bridge Converters With Nonequal DC Link Voltages

Multilevel converters have received increased interest recently as a result of their ability to generate high quality output waveforms with a low switching frequency. This makes them very attractive for high-power applications. A cascaded H-bridge converter (CHB) is a multilevel topology which is formed from the series connection of H-bridge cells. Optimized pulse width modulation techniques such as selective harmonic elimination or selective harmonic mitigation (SHM-PWM) are capable of preprogramming the harmonic profile of the output waveform over a range of modulation indices. Such modulation methods may, however, not perform optimally if the dc links of the CHB are not balanced. This paper presents a new SHM-PWM control strategy which is capable of meeting grid codes even under nonequal dc link voltages. The method is based on the interpolation of different sets of angles obtained for specific situations of imbalance. Both simulation and experimental results are presented to validate the proposed control method.

Selective Protection Analysis Using a SEU Emulator: Testing Protocol and Case Study Over the Leon2 Processor

VLSI circuits for space application must be protected by the insertion of massive redundancy. However, this increases silicon area and the production costs, therefore designers can often consider leaving some large, noncritical subcircuits unprotected. This paper presents how FT-UNSHADES, a nonintrusive tool for fault injection on emulated hardware, helps designers to select the proper level of protection in every subcircuit. Using FT-UNSHADES, a test procedure is proposed that provides: 1) information about the quality of the test vectors, 2) a proper estimation of the number of injected faults required to get confidence about the results of a fault injection campaign, and 3) information about the criticality of individual subcircuits by selective fault injection campaigns. In addition, FT-UNSHADES allows the insertion of multi-bit flips. This test procedure has been applied to three different, protected and unprotected, versions of the well-known Leon2 processor, and the results are discussed here.

FTUNSHADES2: A novel platform for early evaluation of robustness against SEE

Large digital integrated circuits designed to solve space applications, have to be designed following standards that recommend to include hardening techniques against Single Event Phenomena caused by harsh radiation environments. It is specifically important in the case of modern deep-submicron technologies. Single Event Effects are phenomena related to the effects of radiation when ionizing particles hit the surface of semiconductors in certain critical areas, where the consequences are mainly data corruption or unexpected behavior with no permanent damage. Fault injection studies are a valuable methodology to evaluate the robustness of the circuit mainly in the early stages of the design. This paper introduces the second generation of the emulation-based fault injection platform FTUNSHADES supported by the European Space Agency, where new features have been included to fulfill with the demands of a growing community of users.

Implementation of a closed loop SHMPWM technique for three level converters

High power converters are built using high-voltage and high-current rated semiconductors. The commutation of these devices imply large amounts of energy per cycle leading to very low switching frequency in order to avoid a high rise on the semiconductors temperature. The consequence is high harmonic distortion generated by the converter. Grid codes requirements specify the maximum admitted harmonic distortion. The well known selective harmonic elimination pulse width modulation (SHEPWM) technique has proved to be useful in eliminating some of the undesired harmonics without increasing the switching frequency, leaving the rest of them free. The solution to the rest of harmonics is to add bulky and expensive filters. Recently, the method named selective harmonic mitigation pulse width modulation (SHMPWM) has been introduced. The aim of this technique is to mitigate the amplitude of the undesirable harmonics, to acceptable values to meet the grid code, considering a larger number of harmonics. In this paper a practical implementation of this technique in a closed loop scheme is presented. The experimental results using a 150 kW three-level diode-champed converter show that the output signals meet the EN 50160 and CIGRE WG 36-05 grid codes. Comparisons between SHMPWM and SHEPWM are included in the experiments, showing the superior performances of the SHMPWM technique.

Radiation Environment Emulation for VLSI Designs: A Low Cost Platform based on Xilinx FPGA's

As technology shrinks, critical industrial applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as single event effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT- As technology shrinks, critical industrial applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as single event effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT-UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-II. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As a result the system can insert and analyse at least 80 K faults per hour in a system with 2 million test vectors.UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-II. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As a result the system can insert and analyse at least 80 K faults per hour in a system with 2 million test vectors.

Mixed-Mode Simulation of Bit-Flip With Pulsed Laser

This paper shows an adaptation of the Sentaurus TCAD suite to pulsed laser SEE simulation. After the literature review, we present the model of the target transistor, calibrated against the HSPICE model of the foundry. The target model is used to evaluate the Linear Energy Transfer threshold for bit-flip in a simulated flip-flop circuit using the heavy-ion simulation tools of Sentaurus TCAD. Those simulations help us to make an adaptation of Sentaurus TCAD physical model for simulation of pulsed laser experiments. The pulsed laser simulation results are compared with a pulsed laser experiment, showing that the proposed model achieves more accuracy than previous models referred to in the literature.

Pulsed Laser SEU Cross Section Measurement Using Coincidence Detectors

This work presents the determination of a Pulsed Laser SEU Cross-Section (Count Statistics). In this work, a coincidence detector has been used to count fault events by comparing the digital VLSI circuit under test with a replica of the design running on a control FPGA. A SEU is declared when a specific fault pattern is detected. The target chip design generates specific fault patterns under pulsed laser shinning. Sweeping the laser energy on a flip flop of a Shift Register, data for a cross section analysis it is obtained. The coincidence detector was previously tested in a preliminary radiation test, so all the lessons learned in the design of radiation test can be translated for future works. In this work it has been used the pulsed laser facilities of Spanish National Laser Center in Salamanca.

Selective harmonic mitigation technique for multilevel cascaded H-bridge converters

The increasing demand of energy and proliferation of non-linear loads have leaded to the appearance of new grid codes which limit the maximum acceptable harmonic levels. In this context, multilevel topologies are very attractive because can generate output waveforms with a low harmonic content using a low switching frequency. In this paper, the recently presented selective harmonic mitigation technique (SHMPWM) is adapted to a nine-level converter. Its flexibility is exploited to meet the EN 50160 and CIGRE WG 36−05 grid codes without any additional filtering system using 10 switching angles per quarter of period in a wide range of amplitudes of the fundamental harmonic from 0.70 to 1.22. Some results validating this technique applied to this topology are presented. A comparison with the well known selective harmonic elimination method is included showing the advantages of the SHMPWM technique.

TCAD Simulations on CMOS Propagation Induced Pulse Broadening Effect: Dependence Analysis on the Threshold Voltage

Propagation induced pulse broadening (PIPB) effect is becoming a major concern for electronic designers since new technologies are fast enough to propagate and capture Single Event Transients (SET). In this paper, we explore the influence of the MOSFET threshold voltage (VT) on PIPB effect by TCAD simulating the propagation of an SET after an ion strike, showing up this dependence by the modification of some CMOS technology parameters affecting VT. For this work, the test vehicle used to measure PIPB effect is a self-feedback chain of CMOS inverters. The conclusions outlined can be useful when designing with Multi-Vt nano-metric CMOS technologies. Our results suggest that the |VT|/VDD ratio could be a figure of merit for SET propagation broadening.