Hiroaki Himi

Intelligent power IC with partial SOI structure

In the integration of power devices and control circuits, temperature rise caused by the heat dissipation of power devices and electric interference between power devices and control circuits are important problems. In this report, the following was demonstrated by using the partial silicon-on-insulator (SOI) structure with shielding layers. The partial SOI structure has the Si directly bonded areas where power devices are formed and SOI areas where control circuits are formed. Firstly, the temperature rise was reduced to about a half that in the complete SOI structure, and the latch-up occurrence in the control circuit was prevented by the insertion of shielding layers. Secondly, at the condition of 150° C and 16 V, the normal operation of an intelligent power IC consisting of multichannel power devices and a 1-bit microcomputer was accomplished.

Silicon Wafer Direct Bonding without Hydrophilic Native Oxides

Silicon wafer direct bonding was accomplished between two surfaces which had no hydrophilic native oxide layers. Prior to bonding, two wafers were dipped in conc-HF solution ( ~49% aq.) to remove the native oxide layers and then immersed in deionized water. The level of bonding was evaluated by X-ray topography, high resolution transmission electron microscopy (HRTEM) and tensile strength measurement. It was found that the bonded wafer pairs were void-free and had good bonding strength. HRTEM observation showed that the crystal lattice was continuous and had only small distortions and precipitates. Spreading resistance (SR) measurement across the interface showed that the electric resistance did not increase at the bonding interface. It is suggested that the OH groups which substitute the F atoms terminated on the small portion of the surface play an important role in this conc-HF-treated bonding.

Influence of growth pressure on filling 4H-SiC trenches by CVD method

To construct a superjunction structure consisting of p/n columns, narrow stripe-shaped trenches (~1.5 µm wide and ~4.7 µm deep) preformed on an n+ 4H-SiC substrate were filled by the hot-wall CVD method using a conventional gas reaction system, SiH4:C3H8:H2. The influences of growth pressure on the coverage distribution of epilayers and the corresponding filling efficiency (the thickness ratio of epilayers on trench bottom and mesa top) were investigated. Two benefits of increasing the growth pressure from 10 to 38 kPa were found: one is the reduced growth around the mesa surface, which lessens the risk of void formation; the other is a high filling rate as well as an improved filling efficiency up to ~7. By supplying source gases at high flow rates, a void-free trench filling with a filling rate of ~1.3 µm/h was successfully achieved at 38 kPa.

Intelligent power IC for automotive electronics, using trench-dielectric-isolation technology

We developed an intelligent power IC suitable for automotive applications, which integrated CMOS, Bipolar and LDMOS and which was fabricated on 0.65 μm design rule process. This IC employs trench-dielectric-isolation (TD) technology and power device technology that improves the ESD (Electrostatic Discharge) robustness. TD technology employing an SOI (Silicon On Insulator) wafer and deep trench isolation realizes very narrow isolation width with no parasitic device. It enables the easier mixing of various circuits on a single chip with high integration density. The power device technology of improves ESD robustness, enables reduction in the number of protection devices in automotive Electronic control units (ECUs), which connect with the power IC output terminals. Therefore, the intelligent power IC developed here can reduce ECU component numbers and hence ECU size, and is applicable to various kinds of ECUs and smart actuators with high reliability at lower cost.