Hirokatsu Shirahama

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor

A high-speed, low-power and compact processing element (PE) using quaternary differential logic is proposed for a multi-core single-instruction multiple-data (SIMD) processor. A two-bit addition which is the critical path of the ALU is attributed to a one-digit quaternary addition that is directly performed by using multiple-valued current- mode (MVCM) differential logic circuitry. A one-digit quaternary flip-flop is also simply implemented by using the MVCM differential logic circuitry. The efficiency of the proposed quaternary PE is demonstrated using 0.18 mum CMOS HSPICE simulation in comparison with a corresponding CMOS implementation.

Design of High-Performance Quaternary Adders Based on Output-Generator Sharing

Simple implementations of quaternary full adders are proposed for a high-performance multi-processor which consists of many processing elements (PEs). Arbitrary quaternary functions are represented by the combination of input-value conversion and several quaternary output generations. The use of appropriate input-value conversion makes it possible to reduce the number of output generators, which improves the performance of the resulting quaternary full adders. For example, two kinds of single PEs including a quaternary full adder and two flip-flops are implemented using the proposed method and their efficiencies are demonstrated in terms of delay and power dissipation in comparison with those of a corresponding binary CMOS implementation.

Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits

New four-valued logic and static storage components using differential-pair circuits (DPCs) are proposed for a high-performance microprocessor datapath. The DPCbased circuit makes a signal-voltage swing small yet the current-driving capability large, and generates complementary outputs. Both a four-valued comparator and a binary static latch can be merged into a simple DPC-based circuit structure, which achieves low-power dissipation and small chip area while maintaining high-speed switching. As a typical application, a 32-bit microprocessor datapath with five pipelining stages is implemented using the proposed circuit technique in 0.18ìm CMOS, and its advantages are demonstrated in comparison with a corresponding CMOS implementation.

Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System

A dynamic current-source control technique in multiplevalued current-mode (MVCM) circuits is proposed for a power-aware pipelined system. An output monitor in each pipeline stage detects that the combinational logic block has completed a computation for a particular piece of input data and its result has been stored into the pipeline register, and generates “operation-completion” signal. All the current sources in the pipeline stage are cut off by using this control signal. The use of this current-source control technique makes it possible to completely eliminate wasted steady current flow during the rest of clock period, which greedily reduces the power dissipation with maintaining the operating frequency. The efficiency of the proposed technique in a simple MVCM circuit is confirmed using HSPICE simulation under 90nm CMOS. The power dissipation of the MVCM circuit using the proposed technique is always less than that of a corresponding CMOS implementation at the operating frequency of 0.8GHz and more.

Design of a low-power quaternary flip-flop based on dynamic differential logic

A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 μm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.

Design and Evaluation of a 54 54-bit Multiplier Based on Differential-Pair Circuitry

This paper presents a high-speed 54 x 54-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 μm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8V supply occupying a 0.85 mm 2 active area.

Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link

A single-ended-style current-mode circuit with quaternary current signaling is proposed for an energy-efficient asynchronous communication link. The use of quaternary-encoded current signaling and dynamic current-feedback mechanism makes information density twice per wire because of small signal-voltage swing with maintaining high-speed switching capability, which resulting in energy-efficient asynchronous data transmission. It is demonstrated that the proposed link with a 10mm inter-chip transmission line achieves the throughput of 1.1Gbps per wire at the power supply of 1.2V under a 130nm CMOS technology.

Energy-aware current-mode inter-chip link for a dependable GALS NoC platform

An inter-chip communication link with high-speed and low-energy capabilities is proposed for a dependable globally-asynchronous-locally-synchronous (GALS) network-on-chip (NoC) platform. The use of a dynamic current feedback mechanism in the link makes a current driving capability high and a signal voltage swing small, which accelerates the switching speed. The power-gating technique is also applied to greatly reduce the power dissipation since the inter-chip communication links are supposed to have long idle time in the dependable GALS NoC platform. It is demonstrated that the proposed circuit with a 1cm transmission line achieves the transmission rate of 2.8Gbps while consuming 1.1uW in a 130nm CMOS technology at the power supply of 1.2V.

Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link

A single-ended current-mode interface circuit with a single-rail wire is proposed for a high-speed and highly reliable inter-chip communication link in an asynchronous network-on-chip system. The impedance of the single-rail wire is matched to the impedance of the receiver by inserting the MOS transistors, and the current signal level on the link is enlarged in the proposed interface circuit. As a result, crosstalk noise superposed on a single-rail wire can be reduced. It is demonstrated that the noise influences are eliminated under 130nm and 65nm CMOS technologies.