Masanori Natsui

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction

A magnetic tunnel junction (MTJ)-based logic-in-memory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ device model produced by the fabricated test chips. Through the measurement results of the fabricated LSI, this study shows both the impact of the power-gating technique in a fine temporal granularity utilizing the non-volatility of the MTJ device and the effectiveness of the established automated design environment for designing random logic LSI using nonvolatile logic-in-memory.

Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme

A perpendicular magnetic tunnel junction (P-MTJ)-based one-transistor/one-resistor (1T–1R) binary content-addressable memory (CAM) is proposed for a high-density nonvolatile CAM. The proposed CAM cell performs an equality-search operation between an input bit and the corresponding stored bit by detecting the difference of a cell resistance, where the cell resistance is determined by the series connection of one metal–oxide–semiconductor (MOS) transistor and one P-MTJ device. This circuit structure makes it possible to implement a compact nonvolatile CAM cell circuit with 1.25 µm2 of a cell size in a 0.14 µm complementary MOS (CMOS)/P-MTJ process. Moreover, the equality-search operation in a bit-serial fashion is used for great reduction of the activity rate in the proposed CAM cell array, since most of the mismatched words in the CAM are detected by just several higher bits of comparison results in the word circuits. By applying a bit-level fine-grained power gating scheme, a fabricated 64-bit × 128-word nonvolatile CAM achieves high density with maintaining low search energy under 3.1% of activity rate in the cell array.

Fine-Grained Power-Gating Scheme of a Metal–Oxide–Semiconductor and Magnetic-Tunnel-Junction-Hybrid Bit-Serial Ternary Content-Addressable Memory

A fine-grained power-gating scheme combining metal–oxide–semiconductor (MOS) transistors with magnetic-tunnel-junction (MTJ) devices, where storage data still remains even if the power supply is cut off, is proposed for an ultra low-power bit-serial ternary content-addressable memory (TCAM). Once a mismatched result is detected in a sequence of a bit-level equality-search operation, the power supply of all the cells in the word circuit is cut off, which greatly reduces the standby power dissipation in the word circuit. The standby power dissipation of the proposed TCAM in the standby mode is reduced to about 1.2% in comparison with that of a complementary MOS (CMOS)-only-based TCAM. Moreover, the power-delay product of the proposed TCAM is reduced to 15.5% in comparison with that of the corresponding CMOS-only-based TCAM.

Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System

A dynamic current-source control technique in multiplevalued current-mode (MVCM) circuits is proposed for a power-aware pipelined system. An output monitor in each pipeline stage detects that the combinational logic block has completed a computation for a particular piece of input data and its result has been stored into the pipeline register, and generates “operation-completion” signal. All the current sources in the pipeline stage are cut off by using this control signal. The use of this current-source control technique makes it possible to completely eliminate wasted steady current flow during the rest of clock period, which greedily reduces the power dissipation with maintaining the operating frequency. The efficiency of the proposed technique in a simple MVCM circuit is confirmed using HSPICE simulation under 90nm CMOS. The power dissipation of the MVCM circuit using the proposed technique is always less than that of a corresponding CMOS implementation at the operating frequency of 0.8GHz and more.

Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control

A static current-source control technique in a multiple-valued current-mode (MVCM) circuit is proposed for a low-energy pipelined system. A current-control block embedded in each pipeline stage generates current control signals, which minimizes the amount of current flows depending on a given condition. The use of this current-source control technique makes it possible to reduce the power dissipation with maintaining the operating frequency. The efficiency of the proposed technique in a pipelined MVCM multiplier is confirmed by using HSPICE simulation under 0.13um CMOS technology. The MVCM circuit using the proposed technique achieves 65.1% power reduction compared with a conventional MVCM implementation at the operating frequency of 100MHz and 26.5% reduction at 500MHz with 6.88% area overhead.

Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

Novel logic-LSI architecture, “nonvolatile logic-in-memory (NV-LIM) architecture,” where nonvolatile storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.

Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design

A new VLSI CAD environment considering stochastic behavior of MTJ devices is proposed for the evaluation of not only the performance but also the reliability of MTJ/MOS-hybrid logic LSI. The proposed simulator allows users to support the design of MTJ/MOS-hybrid LSI by RTL/gate-level hardware description, whose simulation considering stochastic switching behavior of MTJ device can be done by analog-mixed-signal simulation with de-facto standard EDA tools. Through the design of a nonvolatile logic LSI based on a general purpose 32-bit microprocessor, the impact of the proposed design flow is demonstrated.

Fine-Grain Power-Gating Scheme of a CMOS/MTJ-Hybrid Bit-Serial Ternary Content-Addressable Memory

Research Institute of Electrical Communication (RIEC), Tohoku University 2-1-1 Katahira, Aoba-ku, Sendai 980-8577, JAPAN Phone: +81-22-217-5508, E-mail: zhao-yun@ngc.riec.tohoku.ac.jp Center for Interdisciplinary Research, CIR, Tohoku University Aramaki aza Aoba 6-3, Aoba-ku, Sendai 980-8578, JAPAN Laboratory for Nanoelectronics and Spintronics, RIEC, Tohoku University 2-1-1 Katahira, Aoba-ku, Sendai 980-8577, JAPAN

MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture

Reduction of power consumption and interconnection delay are the two major issues for the next generation very large scale integrated circuits (VLSIs). Drastic increase of static power dissipation due to leakage current is being anticipated in beyond 45 nm complementary metal oxide semiconductor (CMOS) technology [1]. In addition, increase in the length of global-interconnection in advanced VLSIs results in further increase of both power and delay. Logic-in-memory architecture [2], where memory elements are distributed over a logic-circuit plane, combined with nonvolatile memory is expected to realize both ultra-low-power and shorten interconnection delay [3]-[7]. However, in order to fully take advantage of the logic-in-memory architecture, it is important to implement a nonvolatile memory that has a capability of shorter access time below 10 ns, unlimited endurance, scalable write, and small dimension comparable to the employed CMOS technology. The only available candidate of a nonvolatile memory that could satisfy all the above requirements at this stage is the one using magnetic tunnel junction (MTJ) with spin-injection write [8]-[10]. Fig. 1: General structure of an MTJ-based logic-in-memory circuit.