Hirokazu Noma

IMC bonding for 3D interconnection

We performed stacking experiments on Si dies using annular tungsten TSVs (Through Silicon Vias) and Cu studs with low-volume solder micro-bumps. Unlike standard 100-micron C4 (Controlled Collapse Chip Connection) solder balls, very small solder volumes (< 6 microns in height) form IMC (InterMetallic Compounds) in the junctions during the bonding or reflow processes. The two interconnect metallurgies of Cu/Ni/In and Cu/Sn joints were considered for low-volume lead-free solder micro-bumps for 3D integration. A previous study on these metallurgies [5] showed that the Cu/Sn joints form thermally stable intermetallics while in the Cu/Ni/In joints, some indium solder remains unreacted due to the presence of the Ni barriers. The shear testing on the stacked systems showed that the die stacks with Cu/Sn joints exhibit higher shear strengths than those with Cu/Ni/In joints. However the impact shock testing on the systems revealed that the die stacks with Cu/Sn joints are less resistant to mechanical shocks than the systems with Cu/Ni/In joints. This new work focuses on thermal cycle testing of the die stack systems with the Cu/Ni/In and Cu/Sn interconnections. Preliminary thermal cycle testing on the die stack systems with Cu/Ni/In joints showed that the joints are stable against thermal cycle stresses for thousands of cycles. To quickly compare the systems with two metallurgies, we mounted the Si die stacks onto organic substrates to impose additional stresses on the systems. In addition to standard DTC (Deep Thermal Cycle) tests, we also conducted a HAATS (Highly accelerated Air to Air Thermal Shock) test [23] with a short cycle time to reduce the testing time. The DTC and HAATS tests showed that the stacked systems with Cu/Ni/In joints had fewer failures and smaller increases in the electrical resistances of the joints during the tests than the systems with Cu/Sn joints.

Ultrafine-pitch C2 flip chip interconnections with solder-capped Cu pillar bumps

PoP structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 µm or less, an ultra-fine-pitch flip chip interconnection technique is required. C4 flip chip technology is widely used in area array flip chip packages, but it is not suitable in the ultrafine-pitch flip chips because the C4 solder bumps melt and collapse on the wide opening Cu pads. Although the industry uses ultrafine-pitch interconnections between Au stud bumps on a chip and Sn/Ag pre-solder on a carrier, this flip chip technique has two major problems. One is that the need for bumps on both die and carrier drives up material costs. The other is that the long bonding process time required in the individual flip chip bonding process with associated heating and cooling steps demands large investments in equipment. To address these problems, we developed the mount and reflow with no-clean flux processes, and new interconnection techniques were developed with Cu pillars and Sn/Ag solder bumps on Al pads for wirebonding, were developed. It is very easy to control the gap between die and substrate by adjusting the Cu pillar height. Since it is unnecessary to control the collapse of the solder bumps, we call this the C2 process for direct Chip Connection (C2). The C2 bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preservative), with reflow and no-clean processes. This technology creates the SMT/Flip Chip hybrid assembly for SoP (System on Package) use. We have produced 50 µm-pitch C2 interconnections and tested their reliability. The interconnection resistance increase caused by the reliability testing is quite small. It is clear that C2 flip chip technology provides robust solder connections at low cost. Also the C2 structure with a low-k device was evaluated and no failures were observed at 1,500 cycles in the thermal cycle test. This indicates that low-k C2 structures seem robust. For finer pitch flip chip interconnections, a wafer-level underfill process is needed to overcome the limitations of the standard capillary underfill process for ultra-narrow spaces. To date, a wafer- level underfill process exists for the C2 process with an 80-µm pitch. In addition to fine pitch interconnections, a die thickness of 70 µm is required to reduce the final stack height. Such thin die cannot be processed by the C2 process because such dies slip too easily during the reflow process. To resolve this issue, a Post-Encapsulation Grinding (PEG) method was developed. In this method the die is ground to less than 70 µm after joining and underfilling. This report presents the PEG method and reliability test results for die thicknesses 20 µm, 70 µm and 150 µm.

High-Bandwidth Density and Low-Power Optical MCM Using Waveguide-Integrated Organic Substrate

A high-bandwidth density and low-power optical multichip module (MCM) is developed and demonstrated. The module includes bare optical and driver chips and an application specific integrated circuit bonded on an optical waveguide-integrated organic carrier. Characterization results show that the optical I/O operates up to 20 Gb/s. The high-speed performance is not limited by the electrical characteristics of the carrier but by the optical chip bandwidth. The space between the VCSEL/PD surface and the waveguide is minimized to less than 5 μm by using an assembly technology with chip height control, which results in an average insertion loss of 2.7 dB. Alignment tolerances for a 0.5 dB insertion loss increase are ±5 and 7 μm for the transmitter, and ±6 and 7 μm for the receiver in the parallel and perpendicular directions respectively. This type of organic optical MCM promises to integrate high-bandwidth density and low-power optical I/Os with CMOS ICs on first level packages for next generation high performance computers and servers.

Fluxless bonding for fine-pitch and low-volume solder 3-D interconnections

Fluxless bonding can be used for fine-pitch low-solder-volume interconnections for three-dimensional large-scale integrated-circuit (3D-LSI) applications. Surface treatments with hydrogen radicals, formic acid, vacuum ultraviolet (VUV), and Ar plasma were evaluated as candidate methods for fluxless bonding. Three-μm-thick Sn solders were evaluated for intermetallic-compound (IMC) bonding of 3D integration as a target material for fluxless bonding. X-ray photoelectron spectroscopy (XPS), Auger electron spectro-scopy (AES), time-of-flight secondary ion mass spectrometry (TOF-SIMS), a scanning electron microscope (SEM), and a focused ion beam scanning ion microscope (FIB-SIM) were used to examine the samples. The experiments shows solder oxides and organic contaminants on the surfaces of the micro-bumps were most effectively eliminated without flux by hydrogen radical treatment among various treatments we evaluated. Bonding strength was also improved by the hydrogen radical treatment, since the shear strength was more than 50 times stronger than that of the untreated samples.

Injection molded solder - A new fine pitch substrate bumping method

Injection molded soldering (IMS) technology has been developed for solder bumping of fine-pitch organic substrates. Pure molten solder is injected through a flexible film mask that is aligned to the recessed pad openings to form solder bumps on the substrate. The new substrate bumping method is a simple one pass operation for various size pads, with the capability of forming high solder volume on fine pitch substrate.

Electromigration analysis of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump

In this report, the electromigration behavior of 80μm pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with Cu pillars and Sn/Ag capped solder bumps formed on Al pads for wirebonding. The technique was reported in ECTC 2009. It allows an easy control of the space between dies and substrates just by varying the Cu pillar height. The control of the collapse of the solder bumps is not necessary, hence the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow and no-clean process. C2 is a low cost ultra fine pitch Flip Chip interconnection. However, the electromigration behavior for such a small flip chip interconnection is still an open issue. The electromigration tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and pure Sn. The effect of Ni barrier layer on the test is also studied. The tests showed that the presence of IMC layers reduce the atomic migration of Cu. The test also showed that the Ni barrier is also effective in reducing the migration of Cu atoms into Sn solder. The under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm pitch. The die size is 7.3 mm square and the organic substrate is 20 mm square with 4 layers laminated prepreg with 310μm thickness. Electromigration test condition is 7–10 kA/cm2 at 125–170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process which is 2,000 hr at 150°C and then the electromigration tests were performed. We have studied the effect of IMCs thickness on electro-migration induced failure mechanism in C2 flip chip interconnection on an organic substrate.

Electrical design optimization and characterization in Cell Broadband Engine package

Cell Broadband Engine is a microprocessor that has very high processing performance and very high speed I/O to communicate with other devices such as system LSI and memory chips. Design optimization with statistical analysis was carried out. DOE matrix was made with dimension of signal traces and dielectric constant of the insulator in the package substrate. After major factors were detected, random sampling was done to make sure that the distribution of characteristic impedance of signal traces is within the specification. Passive characterization was carried out with test vehicle. Insertion loss and characteristic impedance is dependent on both temperature and water absorption. These environmental factors need to be taken into account when the design rule is determined. After design rule is fixed, circuit simulation for whole signal channel was carried out with considering impedance tolerance in both the package and the printed circuit board. DOE matrix was made and analyzed to determine the major factors on mid-frequency and low-frequency noise in power distribution. Inductance of package substrate and decoupling capacitor are the major effect on the mid-frequency noise, and capacitance of on-module and on-PCB affect low frequency noise. The effect of on-chip parameters was also evaluated. Several types of capacitors were characterized to measure their parasitic parameters

Effect of preformed IMC layer on electromigration of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump

The electromigration (EM) behavior of 80μm pitch C2 (Chip Connection) interconnection [1,2,3] is studied and discussed. C2 is a low cost, peripheral ultra fine pitch flip chip interconnection technology based on the solder capped Cu pillar bumps. The Cu pillar bumps are formed on Al pads that are commonly used in the wirebonding (WB) technique. It thus makes utmost use of the already existing infrastructure. Because C2 bumps are connected to OSP surface treated Cu pads on an organic substrate by reflow with no-clean process, it has a high throughput and is SMT (Surface Mount Technology) compatible. Since the space between dies and substrates is determined by the Cu pillar height, the collapse control of the solder bump is not required. Also, the pre-solder on substrates is also not required. It is an ideal technology for the systems requiring fine pitch structures. Various reliability tests including the thermal cycle tests and thermal humidity bias tests of C2 technology have already been performed. However, only few investigations have been done on the reliability against the EM failures for this technology. In this report, the EM tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and Sn100%. The effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests are studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height is 45μm and the solder height is 25μm. Aged process for pre-formed IMCs was 2,000 hrs at 150°C. The analysis on the samples after the tests showed that the Cu pillar dissociation occurs only in the electron flow direction. However the polarity dependence of IMC layer growths was not detected. C2 test vehicles with pre-formed IMC layers showed no significant electrical resistance increase during the test. Also the consumption of Cu atoms was not observed either from the Cu pillars on the dies or from the Cu pads on the substrates for these test vehicles. The Cu pillar dissociations into the solder were less for the pillars with Ni barrier layers than for those without. The results suggest that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in preventing the Cu atoms from dissociating into the solder. The present study showed a potential ways of forming the Cu pillar joints that are resistant to EM failures.

Chip/Package Design and Technology Trade-offs in the 65nm Cell Broadband Engine

Technology migration of the Cell Broadband Enginetrade (BE) Microprocessor to 65 nm chip technology precipitated a redesign of the original IC packaging. While many of the design changes were necessitated by the chip technology migration, other modifications were implemented to enhance the robustness and overall manufacturability of the product. This paper will discuss key aspects of the 65nm chip technology that drove changes to the package design and also describe some of the modifications to enhance the manufacturability of the product. The paper will outline the statistical analysis, modeling, simulation and characterization employed in the electrical and thermal design, specification and tolerancing of the microprocessor package. The paper will be of specific interest to those involved in the cost-effective, high performance IC package design and development and will be of general interest to those developing and refining analysis methods employed in overall design and technology trade-offs in advanced packaging.

High-bandwidth density optical I/O for high-speed logic chip on waveguide-integrated organic carrier

We demonstrate a high-bandwidth density optical I/O on a waveguide-integrated organic carrier. Each transmitter channel operates at a data rate up to 20 Gb/s for an aggregate value of 240 Gb/s. High-speed and inter-channel crosstalk characterization show that the optical multi-chip module realizes over 10 times higher bandwidth density than conventional optical fiber modules by chip-level packaging and waveguide core pitch reduction, therefore the module supports a nearly 2 Tb/s bandwidth.