Keishi Okamoto

Through silicon via process for effective multi-wafer integration

We propose a novel 3D integration method, called Vertical integration after Stacking (ViaS) process. The process enables 3D integration at significantly low cost, since it eliminates costly processing steps such as chemical vapor deposition used to form inorganic insulator layers and Cu plating used for via filling of vertical conductors. Furthermore, the technique does not require chemical-mechanical polishing (CMP) nor temporary bonding to handle thin wafers. The integration technique consists of forming through silicon via (TSV) holes in pre-multi-stacked wafers (> 2 wafers) which have no initial vertical electrical interconnections, followed by insulation of holes by polymer coating and via filling by molten metal injection. In the technique, multiple wafers are etched at once to form TSV holes followed by coating of the holes by conformal thin polymer layers. Finally the holes are filled by using molten metal injection so that a formation of interlayer connections of arbitrary choice is possible. In this paper, we demonstrate 3-chip-stacked test vehicle with 50 × 50 μm-square TSVs assembled by using this technique.

Electromigration analysis of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump

In this report, the electromigration behavior of 80μm pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with Cu pillars and Sn/Ag capped solder bumps formed on Al pads for wirebonding. The technique was reported in ECTC 2009. It allows an easy control of the space between dies and substrates just by varying the Cu pillar height. The control of the collapse of the solder bumps is not necessary, hence the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow and no-clean process. C2 is a low cost ultra fine pitch Flip Chip interconnection. However, the electromigration behavior for such a small flip chip interconnection is still an open issue. The electromigration tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and pure Sn. The effect of Ni barrier layer on the test is also studied. The tests showed that the presence of IMC layers reduce the atomic migration of Cu. The test also showed that the Ni barrier is also effective in reducing the migration of Cu atoms into Sn solder. The under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm pitch. The die size is 7.3 mm square and the organic substrate is 20 mm square with 4 layers laminated prepreg with 310μm thickness. Electromigration test condition is 7–10 kA/cm2 at 125–170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process which is 2,000 hr at 150°C and then the electromigration tests were performed. We have studied the effect of IMCs thickness on electro-migration induced failure mechanism in C2 flip chip interconnection on an organic substrate.

Electrical characterization of low-cost glass/epoxy laminates at millimeter wave frequencies

We describe the characterization of low-cost glass/epoxy laminates at millimeter-wave frequencies up to 110 GHz. We characterize the loss, dielectric constant and Fiber-Weave-Effect properties of 3 such laminates. We also demonstrate several test cases of transitions at E-band and D-band frequencies (up to 130 GHz) designed with these laminates, showing excellent perform ance.

Effect of preformed IMC layer on electromigration of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump

The electromigration (EM) behavior of 80μm pitch C2 (Chip Connection) interconnection [1,2,3] is studied and discussed. C2 is a low cost, peripheral ultra fine pitch flip chip interconnection technology based on the solder capped Cu pillar bumps. The Cu pillar bumps are formed on Al pads that are commonly used in the wirebonding (WB) technique. It thus makes utmost use of the already existing infrastructure. Because C2 bumps are connected to OSP surface treated Cu pads on an organic substrate by reflow with no-clean process, it has a high throughput and is SMT (Surface Mount Technology) compatible. Since the space between dies and substrates is determined by the Cu pillar height, the collapse control of the solder bump is not required. Also, the pre-solder on substrates is also not required. It is an ideal technology for the systems requiring fine pitch structures. Various reliability tests including the thermal cycle tests and thermal humidity bias tests of C2 technology have already been performed. However, only few investigations have been done on the reliability against the EM failures for this technology. In this report, the EM tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and Sn100%. The effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests are studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height is 45μm and the solder height is 25μm. Aged process for pre-formed IMCs was 2,000 hrs at 150°C. The analysis on the samples after the tests showed that the Cu pillar dissociation occurs only in the electron flow direction. However the polarity dependence of IMC layer growths was not detected. C2 test vehicles with pre-formed IMC layers showed no significant electrical resistance increase during the test. Also the consumption of Cu atoms was not observed either from the Cu pillars on the dies or from the Cu pads on the substrates for these test vehicles. The Cu pillar dissociations into the solder were less for the pillars with Ni barrier layers than for those without. The results suggest that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in preventing the Cu atoms from dissociating into the solder. The present study showed a potential ways of forming the Cu pillar joints that are resistant to EM failures.

HAST failure investigation on ultra-high density lines for 2.1D packages

Silicon interposers have a potential problem which is high cost. Therefore, a 2.1D package using organic material is proposed and the research becomes hot. In this paper, to check whether insulators have enough HAST reliability, biased HAST and unbiased HAST were performed using 40-micron thick insulators. The insulators meet our criteria from both insulation resistance between lines and series resistance points of view in Line/Space 2microns/2microns. Series resistance increase ratio of meander lines depends on the interruption due to putting off from HAST chamber. Therefore, it is preferable to measure the series resistance in-situ in HAST chamber. Based on the experimental results that the series resistance increase was found not only in biased HAST but also in unbiased HAST, a model was proposed. The model is that the series resistance increase is not simply in proportion to electric field strength but in proportion to sum of a fitting parameter and electric field strength. Based on the model, a material with filler may pass our criteria in Line/Space 1micron/1micron in 40-micron thick. Insulation resistance of Line/Space 1micron/1micron need to be evaluated as a future work due to no failure no failure in the experiments down to Line/Space 2microns/2microns during the biased HAST.

Electrical assessment of chip to chip connection for ultra high density organic interposer

Organic interposer which utilize existing manufacturing infrastructure and material, has capability and potential to be in low cost. Furthermore, organic material property which has lower relative dielectric constant (Dk) than silicon dioxide (SiO2) potentially realizes higher bandwidth, keeping particular characteristic impedance on transmission line. In this paper, we focus on a simple chip-to-chip connection with ultra high density circuitry on an organic interposer to make more understanding of relation between trace width and bandwidth. The results show that the bandwidth with assumed organic material is comparable to or more than that with SiO2, and the trace width to obtain bandwidth peak is around 1μm - 2μm.

Electrical capability assessment for high wiring density organic interposer

Silicon and glass interposers provide a solution to keep scaling of C4 dimensions and chip-to-chip interconnect density by supporting high bandwidth. However there are still some challenges in the fabrication process and cost. As another alternative solution, organic material would be a candidate. In order to perform the feasibility study for allowable bandwidth with organic material, various electrical parametric analyses were performed assuming simple chip-to-chip bus connection in the region of less than 10 μm trace width. The results are indicating that the bandwidth with assumed organic material is comparable or more to one with SiO2 material and the trace width to obtain the bandwidth peak is 1-2 μm.

Effect of preformed Cu-Sn IMC layer on electromigration reliability of solder capped Cu pillar bump interconnection on an organic substrate

The electromigration behavior of 80μm pitch solder capped Cu pillar bump interconnection on an organic carrier is studied and discussed. In 2011, the EM tests were performed on 80μm pitch solder capped Cu pillar bump interconnections and the effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests were studied. The EM test conditions of the test vehicles were 7-10 kA/cm2 at 125-170°C. The Cu pillar height was 45μm and the solder height was 25μm. The solder composition was Sn-2.5Ag. Aged condition for pre-formed IMCs was 2,000 hours at 150°C. It was shown that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in reducing the Cu atom dissolution. In this report, it is studied that which of the IMC layers, Cu3Sn or Cu6Sn5, is more effective in preventing the Cu atom dissolution. The cross-sectional analyses of the joints after the 2,000 hours of the test with 7kA/cm2 at 170°C were performed for this purpose. The relationship between the thickness of Cu3Sn IMC layer and the Cu migration is also studied by performing the current stress tests on the joints with controlled Cu3Sn IMC thicknesses. The samples were thermally aged prior to the tests at a higher temperature (200°C) and in a shorter time (10-50 hours) than the previous experiments. The cross-sectional analyses of the Sn-2.5Ag joints without pre-aging consisting mostly of Cu6Sn5, showed a significant Cu dissolution while the Cu dissolution was not detected for the pre-aged joints with thick Cu3Sn layers. A large number of Kirkendall voids were also observed in the joints without pre-aging. The current stress tests on the controlled Cu3Sn joints showed that Cu3Sn layer thickness of more than 1.5μm is effective in reducing Cu dissolution in the joints.

Joint reliability study of solder capped metal pillar bump interconnections on an organic substrate

Flip chip technology is widely used on the electronic packaging, and the market forces drive toward finer pitch interconnection. Cu pillar bump structure is a currently trend of the fine pitch flip chip package with less than 100μm bump pitch. But there is a solder volume limitation on solder capped Cu pillar bump structure. In addition, Cu may easily react with Sn-based solder into intermetallic compounds (IMCs). So it may be difficult for much finer pitch application with the structure. In this paper, we studied the fine pitch (50μm) flip chip interconnections with various bump structures and the die thickness. The 3-types of solder capped metal (Cu, Cu-Ni and Ni) pillar bumps and the 3-different die thickness (100μm, 300μm and 725μm) were evaluated. Finite Element Method (FEM) simulation was performed to analyze the thermal mechanical stress on the solder joint and on the root of metal pillar first. The result showed that the stress on the root of pillar on Ni pillar bump was higher than that of Cu pillar bump, and the stress on solder joint and the root of pillar was reduced by thinning the die thickness. To verify these results, the initial solder joints were observed using an optical microscope and a Scanning Electron Microscope (SEM). The IMC phases, the IMC growth and the interconnect microstructures were compared. After these observations, a thermal cycling test (Condition : -55°C/+125°C) was performed, then the lifetime was compared between Cu pillar bump and Ni pillar bump. In the study, we obtained good reliability data on both pillars, but the lifetime of Cu pillar bumps was 1.5 times better than that of Ni pillar bump with the same structure. In addition, the electro-migration (EM) test was performed to investigate the EM behavior of microjoints on Cu pillar bump and Ni pillar bump. In the study, there is no significant difference on the electrical resistance variation until 2,000hrs.

Solder Injected through Via for Multi Stacked Wafers

Low cost through silicon via (TSV) technology is a key enabler for the future performance growth of various semiconductor devices. Deep etching and solder filling for TSV through pre-stacked silicon wafers make the TSV process much simpler. Polymer insulator also contributes to stress reduction and conformal insulation. In this paper, we investigate the barrier effect of polymer insulators on metal diffusion through the polymer into a silicon device by using various simple test specimens. It is found that although tin and indium showed some diffusion in the polymer materials, gold, silver, and bismuth showed little diffusion after excess annealing. We conclude that various popular solders such as SnAg, SnBi, and SnIn can be adopted as the solder via material with low risk of metal contamination in silicon.