Kazushige Toriyama

Ultrafine-pitch C2 flip chip interconnections with solder-capped Cu pillar bumps

PoP structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 µm or less, an ultra-fine-pitch flip chip interconnection technique is required. C4 flip chip technology is widely used in area array flip chip packages, but it is not suitable in the ultrafine-pitch flip chips because the C4 solder bumps melt and collapse on the wide opening Cu pads. Although the industry uses ultrafine-pitch interconnections between Au stud bumps on a chip and Sn/Ag pre-solder on a carrier, this flip chip technique has two major problems. One is that the need for bumps on both die and carrier drives up material costs. The other is that the long bonding process time required in the individual flip chip bonding process with associated heating and cooling steps demands large investments in equipment. To address these problems, we developed the mount and reflow with no-clean flux processes, and new interconnection techniques were developed with Cu pillars and Sn/Ag solder bumps on Al pads for wirebonding, were developed. It is very easy to control the gap between die and substrate by adjusting the Cu pillar height. Since it is unnecessary to control the collapse of the solder bumps, we call this the C2 process for direct Chip Connection (C2). The C2 bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preservative), with reflow and no-clean processes. This technology creates the SMT/Flip Chip hybrid assembly for SoP (System on Package) use. We have produced 50 µm-pitch C2 interconnections and tested their reliability. The interconnection resistance increase caused by the reliability testing is quite small. It is clear that C2 flip chip technology provides robust solder connections at low cost. Also the C2 structure with a low-k device was evaluated and no failures were observed at 1,500 cycles in the thermal cycle test. This indicates that low-k C2 structures seem robust. For finer pitch flip chip interconnections, a wafer-level underfill process is needed to overcome the limitations of the standard capillary underfill process for ultra-narrow spaces. To date, a wafer- level underfill process exists for the C2 process with an 80-µm pitch. In addition to fine pitch interconnections, a die thickness of 70 µm is required to reduce the final stack height. Such thin die cannot be processed by the C2 process because such dies slip too easily during the reflow process. To resolve this issue, a Post-Encapsulation Grinding (PEG) method was developed. In this method the die is ground to less than 70 µm after joining and underfilling. This report presents the PEG method and reliability test results for die thicknesses 20 µm, 70 µm and 150 µm.

Through silicon via process for effective multi-wafer integration

We propose a novel 3D integration method, called Vertical integration after Stacking (ViaS) process. The process enables 3D integration at significantly low cost, since it eliminates costly processing steps such as chemical vapor deposition used to form inorganic insulator layers and Cu plating used for via filling of vertical conductors. Furthermore, the technique does not require chemical-mechanical polishing (CMP) nor temporary bonding to handle thin wafers. The integration technique consists of forming through silicon via (TSV) holes in pre-multi-stacked wafers (> 2 wafers) which have no initial vertical electrical interconnections, followed by insulation of holes by polymer coating and via filling by molten metal injection. In the technique, multiple wafers are etched at once to form TSV holes followed by coating of the holes by conformal thin polymer layers. Finally the holes are filled by using molten metal injection so that a formation of interlayer connections of arbitrary choice is possible. In this paper, we demonstrate 3-chip-stacked test vehicle with 50 × 50 μm-square TSVs assembled by using this technique.

Wafer IMS (Injection molded solder) — A new fine pitch solder bumping technology on wafers with solder alloy composition flexibility

In this paper, we will describe a new low cost solder bumping technology for use on wafers. The wafer IMS (injection molded solder) process can form fine pitch solder bumps on wafers, while offering greater solder alloy flexibility. This method is also applicable to form uniform solder bump heights when a wafer has different size and shape of I/O pads. The wafer IMS bumping process uses a solder injection head that melts the desired bulk solder alloy composition and then dispenses the molten solder into resist material cavities on wafers within a nitrogen environment. The injected molten solder contacts and wets to the metal pads without flux, thus forming intermetallic compounds at the solder/pad interface. After stripping the resist material, solder bumps exhibit straight side walls and round tops as the solders have solidified inside the cavities of this resist film. This particular geometry is unique and offers a ready-for-substrate bonding condition without an additional reflow step. In the case of using Cu pillars, one resist material is used for both Cu electroplating and molten solder injection. After patterning the resist material, the Cu pillars are electroplated to the desired height, and the remaining cavities of resist material are filled by the injection of molten solder. The final bump height is defined by the thickness of the resist material. Therefore, any non-uniformity of Cu pillar height across a wafer is masked by the final solder bump uniformity. A prototype tool for wafer IMS bumping technology has been developed and solder bumping has successfully been demonstrated with Sn-3.0Ag-0.5Cu solder on 200mm wafers. The test wafer employed interconnects pads of four different diameters and three different shapes. Other solder compositions have also been tried successfully.

High-Bandwidth Density and Low-Power Optical MCM Using Waveguide-Integrated Organic Substrate

A high-bandwidth density and low-power optical multichip module (MCM) is developed and demonstrated. The module includes bare optical and driver chips and an application specific integrated circuit bonded on an optical waveguide-integrated organic carrier. Characterization results show that the optical I/O operates up to 20 Gb/s. The high-speed performance is not limited by the electrical characteristics of the carrier but by the optical chip bandwidth. The space between the VCSEL/PD surface and the waveguide is minimized to less than 5 μm by using an assembly technology with chip height control, which results in an average insertion loss of 2.7 dB. Alignment tolerances for a 0.5 dB insertion loss increase are ±5 and 7 μm for the transmitter, and ±6 and 7 μm for the receiver in the parallel and perpendicular directions respectively. This type of organic optical MCM promises to integrate high-bandwidth density and low-power optical I/Os with CMOS ICs on first level packages for next generation high performance computers and servers.

Fluxless bonding for fine-pitch and low-volume solder 3-D interconnections

Fluxless bonding can be used for fine-pitch low-solder-volume interconnections for three-dimensional large-scale integrated-circuit (3D-LSI) applications. Surface treatments with hydrogen radicals, formic acid, vacuum ultraviolet (VUV), and Ar plasma were evaluated as candidate methods for fluxless bonding. Three-μm-thick Sn solders were evaluated for intermetallic-compound (IMC) bonding of 3D integration as a target material for fluxless bonding. X-ray photoelectron spectroscopy (XPS), Auger electron spectro-scopy (AES), time-of-flight secondary ion mass spectrometry (TOF-SIMS), a scanning electron microscope (SEM), and a focused ion beam scanning ion microscope (FIB-SIM) were used to examine the samples. The experiments shows solder oxides and organic contaminants on the surfaces of the micro-bumps were most effectively eliminated without flux by hydrogen radical treatment among various treatments we evaluated. Bonding strength was also improved by the hydrogen radical treatment, since the shear strength was more than 50 times stronger than that of the untreated samples.

Injection molded solder - A new fine pitch substrate bumping method

Injection molded soldering (IMS) technology has been developed for solder bumping of fine-pitch organic substrates. Pure molten solder is injected through a flexible film mask that is aligned to the recessed pad openings to form solder bumps on the substrate. The new substrate bumping method is a simple one pass operation for various size pads, with the capability of forming high solder volume on fine pitch substrate.

Electromigration analysis of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump

In this report, the electromigration behavior of 80μm pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with Cu pillars and Sn/Ag capped solder bumps formed on Al pads for wirebonding. The technique was reported in ECTC 2009. It allows an easy control of the space between dies and substrates just by varying the Cu pillar height. The control of the collapse of the solder bumps is not necessary, hence the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow and no-clean process. C2 is a low cost ultra fine pitch Flip Chip interconnection. However, the electromigration behavior for such a small flip chip interconnection is still an open issue. The electromigration tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and pure Sn. The effect of Ni barrier layer on the test is also studied. The tests showed that the presence of IMC layers reduce the atomic migration of Cu. The test also showed that the Ni barrier is also effective in reducing the migration of Cu atoms into Sn solder. The under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm pitch. The die size is 7.3 mm square and the organic substrate is 20 mm square with 4 layers laminated prepreg with 310μm thickness. Electromigration test condition is 7–10 kA/cm2 at 125–170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process which is 2,000 hr at 150°C and then the electromigration tests were performed. We have studied the effect of IMCs thickness on electro-migration induced failure mechanism in C2 flip chip interconnection on an organic substrate.

Electrical characterization of low-cost glass/epoxy laminates at millimeter wave frequencies

We describe the characterization of low-cost glass/epoxy laminates at millimeter-wave frequencies up to 110 GHz. We characterize the loss, dielectric constant and Fiber-Weave-Effect properties of 3 such laminates. We also demonstrate several test cases of transitions at E-band and D-band frequencies (up to 130 GHz) designed with these laminates, showing excellent perform ance.

Effect of preformed IMC layer on electromigration of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump

The electromigration (EM) behavior of 80μm pitch C2 (Chip Connection) interconnection [1,2,3] is studied and discussed. C2 is a low cost, peripheral ultra fine pitch flip chip interconnection technology based on the solder capped Cu pillar bumps. The Cu pillar bumps are formed on Al pads that are commonly used in the wirebonding (WB) technique. It thus makes utmost use of the already existing infrastructure. Because C2 bumps are connected to OSP surface treated Cu pads on an organic substrate by reflow with no-clean process, it has a high throughput and is SMT (Surface Mount Technology) compatible. Since the space between dies and substrates is determined by the Cu pillar height, the collapse control of the solder bump is not required. Also, the pre-solder on substrates is also not required. It is an ideal technology for the systems requiring fine pitch structures. Various reliability tests including the thermal cycle tests and thermal humidity bias tests of C2 technology have already been performed. However, only few investigations have been done on the reliability against the EM failures for this technology. In this report, the EM tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and Sn100%. The effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests are studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height is 45μm and the solder height is 25μm. Aged process for pre-formed IMCs was 2,000 hrs at 150°C. The analysis on the samples after the tests showed that the Cu pillar dissociation occurs only in the electron flow direction. However the polarity dependence of IMC layer growths was not detected. C2 test vehicles with pre-formed IMC layers showed no significant electrical resistance increase during the test. Also the consumption of Cu atoms was not observed either from the Cu pillars on the dies or from the Cu pads on the substrates for these test vehicles. The Cu pillar dissociations into the solder were less for the pillars with Ni barrier layers than for those without. The results suggest that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in preventing the Cu atoms from dissociating into the solder. The present study showed a potential ways of forming the Cu pillar joints that are resistant to EM failures.

Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration

A low-cost assembly method is necessary for widespread use of 3D silicon integration. We have been proposing a vertical Si integration process, called Vertical integration after Stacking (ViaS), intended to lower costs, lower stress, and increase yields. The ViaS process uses a polymer insulator and a solder filling technique instead of a SiO2 insulator and Cu plating. Different from conventional processes, each vertical electrical conductor is continuous from the bottom to the top through the silicon stack and the conductor is surrounded with polymer insulators with a low-Youngs modulus. As a result, this ViaS process will greatly decrease the stress in vertical conductors and silicon substrates and increase reliability. In this paper, we present prototyped Si stacks with the ViaS process and the analyzed results on their stress characteristics. The results obtained show significant stress reductions at vertical connections between the layers, which would increase the reliability. These features of 3D stacks by the ViaS process will significantly contribute to expanding the range of 3D-integrated device applications.