Sayuri Kohara

IMC bonding for 3D interconnection

We performed stacking experiments on Si dies using annular tungsten TSVs (Through Silicon Vias) and Cu studs with low-volume solder micro-bumps. Unlike standard 100-micron C4 (Controlled Collapse Chip Connection) solder balls, very small solder volumes (< 6 microns in height) form IMC (InterMetallic Compounds) in the junctions during the bonding or reflow processes. The two interconnect metallurgies of Cu/Ni/In and Cu/Sn joints were considered for low-volume lead-free solder micro-bumps for 3D integration. A previous study on these metallurgies [5] showed that the Cu/Sn joints form thermally stable intermetallics while in the Cu/Ni/In joints, some indium solder remains unreacted due to the presence of the Ni barriers. The shear testing on the stacked systems showed that the die stacks with Cu/Sn joints exhibit higher shear strengths than those with Cu/Ni/In joints. However the impact shock testing on the systems revealed that the die stacks with Cu/Sn joints are less resistant to mechanical shocks than the systems with Cu/Ni/In joints. This new work focuses on thermal cycle testing of the die stack systems with the Cu/Ni/In and Cu/Sn interconnections. Preliminary thermal cycle testing on the die stack systems with Cu/Ni/In joints showed that the joints are stable against thermal cycle stresses for thousands of cycles. To quickly compare the systems with two metallurgies, we mounted the Si die stacks onto organic substrates to impose additional stresses on the systems. In addition to standard DTC (Deep Thermal Cycle) tests, we also conducted a HAATS (Highly accelerated Air to Air Thermal Shock) test [23] with a short cycle time to reduce the testing time. The DTC and HAATS tests showed that the stacked systems with Cu/Ni/In joints had fewer failures and smaller increases in the electrical resistances of the joints during the tests than the systems with Cu/Sn joints.

Development of vacuum underfill technology for a 3D chip stack

We developed a vacuum underfill technology for 3D chip stacks and for flip chips in high performance system integration. We fabricated a 3D prototype chip stack using the vacuum underfill technology to apply the adhesive. The underfill was injected into each 6 µm gaps in a 3-layer chip stack and no voids were detected in acoustic microscopy images. Electrical tests and thermal reliability tests were used to measure the resistance of the vertical interconnections and the impact of the underfill. The results showed there was minimal difference in the average interconnection resistance of the chip stack with and without underfill.

Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package

Rbased on finite element method (FEM) was used to simulate the effects of voids formed inside Cu TSVs on the thermal conduction and mechanical stresses in the TSV structure. The thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses in the TSV structure in 3D SiP were carried out under thermal condition due to power ON/ OFF of device. In case that void was not present inside the TSV, the stresses in TSV were close to the hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. Maximum principal stress of the Si chip in the TSV structure for the case without voids was lower than that of the bending strength of silicon. However, the level of the stresses in the Si chips should not be negligible for damages to Si chips. In case that void was present inside the TSV, stress concentration was occurred around the void in the TSV. The magnitude of the equivalent stress in the TSV was lower than the yield stress of copper. The magnitude of the maximum principal stress of the Si chip was lower than that of the bending strength of silicon. However, its level should not be negligible for damages to TSVs and Si chips. The stress on inner surfaces of Si chip was slightly reduced due to the presence of a void in the TSV. [DOI: 10.1115/1.4006515]

Through silicon via process for effective multi-wafer integration

We propose a novel 3D integration method, called Vertical integration after Stacking (ViaS) process. The process enables 3D integration at significantly low cost, since it eliminates costly processing steps such as chemical vapor deposition used to form inorganic insulator layers and Cu plating used for via filling of vertical conductors. Furthermore, the technique does not require chemical-mechanical polishing (CMP) nor temporary bonding to handle thin wafers. The integration technique consists of forming through silicon via (TSV) holes in pre-multi-stacked wafers (> 2 wafers) which have no initial vertical electrical interconnections, followed by insulation of holes by polymer coating and via filling by molten metal injection. In the technique, multiple wafers are etched at once to form TSV holes followed by coating of the holes by conformal thin polymer layers. Finally the holes are filled by using molten metal injection so that a formation of interlayer connections of arbitrary choice is possible. In this paper, we demonstrate 3-chip-stacked test vehicle with 50 × 50 μm-square TSVs assembled by using this technique.

Electromigration analysis of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump

In this report, the electromigration behavior of 80μm pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with Cu pillars and Sn/Ag capped solder bumps formed on Al pads for wirebonding. The technique was reported in ECTC 2009. It allows an easy control of the space between dies and substrates just by varying the Cu pillar height. The control of the collapse of the solder bumps is not necessary, hence the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow and no-clean process. C2 is a low cost ultra fine pitch Flip Chip interconnection. However, the electromigration behavior for such a small flip chip interconnection is still an open issue. The electromigration tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and pure Sn. The effect of Ni barrier layer on the test is also studied. The tests showed that the presence of IMC layers reduce the atomic migration of Cu. The test also showed that the Ni barrier is also effective in reducing the migration of Cu atoms into Sn solder. The under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm pitch. The die size is 7.3 mm square and the organic substrate is 20 mm square with 4 layers laminated prepreg with 310μm thickness. Electromigration test condition is 7–10 kA/cm2 at 125–170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process which is 2,000 hr at 150°C and then the electromigration tests were performed. We have studied the effect of IMCs thickness on electro-migration induced failure mechanism in C2 flip chip interconnection on an organic substrate.

Bonding technologies for chip level and wafer level 3D integration

This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm2. Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 μm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.

Effect of preformed IMC layer on electromigration of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump

The electromigration (EM) behavior of 80μm pitch C2 (Chip Connection) interconnection [1,2,3] is studied and discussed. C2 is a low cost, peripheral ultra fine pitch flip chip interconnection technology based on the solder capped Cu pillar bumps. The Cu pillar bumps are formed on Al pads that are commonly used in the wirebonding (WB) technique. It thus makes utmost use of the already existing infrastructure. Because C2 bumps are connected to OSP surface treated Cu pads on an organic substrate by reflow with no-clean process, it has a high throughput and is SMT (Surface Mount Technology) compatible. Since the space between dies and substrates is determined by the Cu pillar height, the collapse control of the solder bump is not required. Also, the pre-solder on substrates is also not required. It is an ideal technology for the systems requiring fine pitch structures. Various reliability tests including the thermal cycle tests and thermal humidity bias tests of C2 technology have already been performed. However, only few investigations have been done on the reliability against the EM failures for this technology. In this report, the EM tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and Sn100%. The effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests are studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height is 45μm and the solder height is 25μm. Aged process for pre-formed IMCs was 2,000 hrs at 150°C. The analysis on the samples after the tests showed that the Cu pillar dissociation occurs only in the electron flow direction. However the polarity dependence of IMC layer growths was not detected. C2 test vehicles with pre-formed IMC layers showed no significant electrical resistance increase during the test. Also the consumption of Cu atoms was not observed either from the Cu pillars on the dies or from the Cu pads on the substrates for these test vehicles. The Cu pillar dissociations into the solder were less for the pillars with Ni barrier layers than for those without. The results suggest that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in preventing the Cu atoms from dissociating into the solder. The present study showed a potential ways of forming the Cu pillar joints that are resistant to EM failures.

Thermal stress analysis of 3D die stacks with low-volume interconnections

Silicon die stacking with low-volume interconnections is an attractive method for 3D integration. It offers such benefits as extension to fine-pitch integration, increased vertical heat transfer and hierarchy for repeated thermal processes without re-melting. The process uses low-volume solder to form joints of few microns high. The low-volume solder mostly forms intermetallic compounds with underlying metals. The fomration of intermetallic compounds increases the strength of the solder joints. However the joints formed by intermetallic compounds can be brittle and less resistant to mechanical shocks as compared to the joints mostly formed by pure solder. The joints mechanical properties play an important role in the systems reliability. Therefore in-depth evaluations of joints mechanical properties are crucial to further advance this technology. We considered two metallurgies with different mechanical properties for interconnections between silicon dies: Cu/Sn and Cu/Ni/In. Earlier article reported that the Cu/Sn joints has a higher shear strength than the Cu/Ni/In joints. However the Cu/Ni/In joints showed better a result in the impact shock testing. In this report, we conducted the thermal cycle tests on the silicon die stack systems with the two joint metallurgies. The thermal cycle tests showed that the Cu/Ni/In joint systems have less failures than the systems with Cu/Sn joints. The energy dispersive X-ray (EDX) analyses of the solder joints after the 2250 cycles of thermal cycle tests showed that the CuSn intermetallic compounds dominate the Cu/Sn joint whereas the region of mostly pure indium region still remains in the Cu/Ni/In joints even after the tests. We also conducted a finite element analysis of the Si die stack with the Cu/Sn joints on an organic substrate. The analysis showed that increasing the Si interposer thickness can reduce stresses in the intermetallic compound joints.

Fine-pitch solder joining for high density interconnection

We have studied a thermo-compression bonding method for high density interconnections. Fluxes are commonly used in conventional solder bonding. However, flux applications have several issues such as the void generation in solder and the flux residue remaining between bumps. These could degrade their reliabilities seriously when the bump pitch becomes small since these features do not scale to bump-pitch dimensions. In this paper, we present the experimental results on the investigation of flux-less bonding with a hydrogen radical plasma treatment in fine-pitch bump joining, in order to eliminate these issues. Experimental results of 10 μm-pitch solder bonding showed good metallic continuities at joining interfaces without any organic residues, showing advantages of flux-less bonding on fine-pitch solder bonding.

Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration

The thermo-mechanical reliability of stacked die structures is a critical issue in 3D packaging. The assessment of the stress and the warpage of silicon dies in 3D stacked structures become important in achieving low-stress and low-warpage 3D packaging. However the parametric analyses of thermal stress and die-warpage by rigorous finite element analysis can be time consuming for 3D systems, since it involves many layers of materials such as silicon dies and organic layers. In this paper, we used the finite element method (FEM) with a simple 2D model to analyze the stress under thermal cycling condition on the die stack system and applied the 1D multilayered beam theory to perform parametric analyses of the die-warpage for the thermal stress condition. We used a 3D slice model to analyze the stress in the intermetallic compound (IMC) joints. The die-warpage values and the high stress sites in stacked structures obtained by these analyses were consistent with the measured data and experimental observations from the thermal cycle tests on full-area-array 40 μm bump pitch stacked die test vehicles with intermetallic compound joints.