Hiroki Ishikuro

Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals

Charge storage characteristics have been investigated in metal-oxide-semiconductor memory structures based on silicon nanocrystals, where various interface traps and defects were introduced by thermal annealing treatment. The observations demonstrate that traps have strong influence on the charge storage behavior, in which the traps and defects at the internal/surface of silicon nanocrystals and the interface states at the SiO2/Si substrate play different roles, respectively. It is suggested that the injected charges are mainly stored at the deep traps of nanocrystals instead of the conduction band in long-term retention mode. The long-term charge-loss process is dominantly determined by the direct tunneling of the trapped charges to the interface states in the present experiment. An optimum way to improve the retention time would be to introduce a certain number of deep trapping centers in nanocrystals and to decrease the interface states at SiO2/Si substrate.

Quantum mechanical effects in the silicon quantum dot in a single-electron transistor

The quantum mechanical effects in silicon single-electron transistors have been investigated. The devices have been fabricated in the form of point contact metal–oxide–semiconductor field-effect transistors with various channel widths using electron beam lithography and the anisotropic etching technique on silicon-on-insulator substrates. The device with an extremely narrow channel shows Coulomb blockade oscillations at room temperature. At low temperatures, negative differential conductances and fine structures are superposed on the device characteristics, which are attributed to the quantum mechanical effects in the silicon quantum dot in the channel. The energy spectrum of the dot is extracted from the experimental results.

Coulomb blockade oscillations at room temperature in a Si quantum wire metal-oxide-semiconductor field-effect transistor fabricated by anisotropic etching on a silicon-on-insulator substrate

We have developed a very controllable fabrication process of an extremely narrow (∼10 nm) quantum wire metal‐oxide‐semiconductor field‐effect transistor (MOSFET) on a separation‐by‐implanted‐oxygen (SIMOX) substrate using anisotropic etching and selective oxidation technique. The drain current versus gate voltage characteristics show oscillations caused by Coulomb blockade even at room temperature. The oscillations split into several sharp peaks when the temperature is decreased, indicating that the channel is separated by several serial coupled quantum dots and that the quantum levels of these dots correspond to the observed fine peaks.

Control of Coulomb blockade oscillations in silicon single electron transistors using silicon nanocrystal floating gates

We have fabricated single-electron transistors (SETs) with Si nanocrystal floating gates, and experimentally demonstrated the control of the peak positions of Coulomb blockade oscillations. The positive voltage applied to the gate makes channel electrons tunnel into the floating dots, and the injected electrons raise the potential of quantum dots in SET, resulting in a shift of peak positions of Coulomb blockade oscillations. In addition, from the temperature dependence of device characteristics, it is confirmed that the potential fluctuations caused by random distribution of the Si nanocrystals have a slight influence on the shape of the Ids-Vg curves at practical high temperatures.

On the origin of tunneling barriers in silicon single electron and single hole transistors

To clarify the channel potential profiles, Coulomb blockades of single electron and single hole tunneling in Si nanosize narrow channel metal–oxide–semiconductor field-effect transistors are intensively studied. Devices with both n+ and p+ source/drain contacts were fabricated on silicon-on-insulator substrates. Transport properties of a hole system as well as an electron system induced in the same channel were investigated. It is found from the experimental results that potential fluctuations in the channel act as tunnel barriers for both electrons and holes. Lateral quantum confinement effects or silicon oxide (SiOx) are thought to be the cause of tunnel barriers.

Large Electron Addition Energy above 250 meV in a Silicon Quantum Dot in a Single-Electron Transistor

We demonstrate large Coulomb blockade oscillations in a silicon single-electron transistor (Si SET) whose peak-to-valley ratio is about 2 at room temperature. The device is fabricated in the form of a point-contact metal-oxide-semiconductor field-effect transistor (MOSFET) and the gate oxide is formed by chemical vapor deposition (CVD) instead of thermal oxidation. From the analysis of current-voltage characteristics, it is found that the single-electron addition energy is about 259 meV and the dot diameter is less than 4.4 nm. The mechanism of silicon dot formation is also discussed.

Effects of Interface Traps on Charge Retention Characteristics in Silicon-Quantum-Dot-Based Metal-Oxide-Semiconductor Diodes.

We have demonstrated the effects of interface traps and defects on the charge retention characteristics in silicon-quantum-dot (Si-QDs)-based metal-oxide-semiconductor (MOS) memory structures. MOS diodes with various interface traps and defects introduced by thermal annealing treatment are investigated using a capacitance-voltage (C-V) measurement technique. The model of deep trapping centers including three-dimensional quantum confinement and Coulomb charge effects has been developed to successfully explain the observed long-term charge retention behaviors.

Impact of the device scaling on the low-frequency noise in n-MOSFETs

Abstract.The impact of device scaling on modern MOS technology is discussed in terms of the random telegraph signals (RTSs) and low-frequency noise in n-MOSFETs with gradually decreased channel widths. RTSs with very large amplitude (>60%) are observed in the devices with ultra-narrow channels at room temperature for the first time. Furthermore, low-frequency noise spectra having both 1/f′ and Lorentzian type are found separately in the same ultra-narrow channel at different gate bias voltage, whereas only 1/f′ noise is observed in relatively wide channels. The observations strongly suggest that low-frequency noise in weak inversion dominantly suffer from carrier mobility fluctuation rather than carrier number fluctuation in ultra-narrow channels, which is confirmed by numerical simulations.

SUPPRESSION OF GEOMETRIC COMPONENT OF CHARGE PUMPING CURRENT IN THIN FILM SILICON ON INSULATOR METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS

A new reverse pulse method is proposed for precise measurement of charge pumping current in silicon on insulator metal-oxide-semiconductor field-effect transistors (SOI MOSFETs), where the reverse pulse voltage is applied to the body only at the gate voltage rise time. The majority carries of the high resistive body region can be completely removed by applying the reverse pulse to the body. Therefore, the undesirable, geometry-dependent component which causes imprecise measurement of the interface trap density on SOI MOSFETs is suppressed. This method also suppresses the reduction of effective channel length which takes place when using a DC reverse bias. It is demonstrated that the accurate measurements of the interface density on SOI MOSFETs are possible.

CHARACTERISTICS OF NARROW CHANNEL MOSFET MEMORY BASED ON SILICON NANOCRYSTALS

Metal-oxide-semiconductor field-effect transistor (MOSFET) memory devices with silicon-nanocrystal-based floating gates on a narrow channel have been fabricated. Electrical measurements have been performed in the temperature range of 20–300 K for devices of various channel dimensions. Large threshold voltage shifts are obtained, being obviously dependent on channel width, and independent of channel length. It is experimentally found that the threshold voltage shift and charge retention characteristics are almost independent of temperature. Furthermore, single electron charge/discharge processes are observed in the device with the narrowest channel.