Tadahiro Kuroda

A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

This two-dimensional 8/spl times/8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV-resolution in a 0.3 /spl mu/m CMOS triple-well double-metal technology operates at 150 MHz from a 0.9 V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3 V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed, standby power and chip area.

Variable supply-voltage scheme for low-power high-speed CMOS digital design

This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-/spl mu/m CMOS technology which optimally controls the internal supple voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

This MPEG4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is summarized. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. A 16b RISC processor provides software programmability. Binary shape decoding uses 20% of the computation power of the RISC processor at 30MHz clock, with negligible increase in chip power dissipation. Three-step hierarchical motion estimation reduces power dissipation.

A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

A novel design technique which combines a variable supply-voltage scheme and a clustered voltage scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay and area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit performance compared to a conventional CMOS design.

A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits non-return-to-zero signaling are developed. Test chips stacked at a distance of 300/spl mu/m communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35/spl mu/m CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

Utilizing surplus timing for power reduction

Multiple Vdds, multiple Vths, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdds, Vths, and Ws are derived, as well as knowledge for future design.

Split capacitor DAC mismatch calibration in successive approximation ADC

A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.

A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping

A transceiver for inductive-coupling is realized. By using a pulse-shaping circuit, the transmitter energy is 0.11pj/b. Due to device scaling from 180nm CMOS to 90nm CMOS, the receiver energy is 0.03pJ/b. The overall energy dissipation is 20times lower than previous work, without degrading the data rate of 1Gb/s.

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver

A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM

A 240 mW single-chip MPEG-4 video-phone LSI with a 16 Mb embedded DRAM is fabricated in a 0.25 /spl mu/m CMOS, triple-well, quad-metal technology. The chip integrates a 16 Mb DRAM and three dedicated 16 b RISC processors with dedicated hardware accelerators that serve as an MPEG-4 video codec, a speech codec, and a multiplexer. It also integrates camera, display, and audio interfaces required for a video-phone system. It consumes 240 mW at 60 MHz operation, which is only 22% of the power dissipation of a conventional design. A variable threshold voltage CMOS (VTCMOS) technology is employed to reduce standby leakage current to 26 /spl mu/A, which is only 17% of the conventional CMOS design.