Hiroki Mouri

Robust Read Channel System Directly Processing Asynchronous Sampling Data

In this study, we describe a robust read channel employing a novel timing recovery system and a unique Viterbi detector which extracts channel timing and channel data directly from asynchronous sampling data. The timing recovery system in the proposed read channel has feed-forward architecture and consists entirely of digital circuits. Thus, it enables robust timing recovery at high-speed and has no performance deterioration caused by variations in analog circuits. The Viterbi detector not only detects maximum-likelihood data using a reference level generator, but also transforms asynchronous data into pseudosynchronous data using two clocks, such as an asynchronous clock generated by a frequency synthesizer and a pseudosynchronous clock generated by a timing detector. The proposed read channel has achieved a constant and fast frequency acquisition time against initial frequency error and has improved its bit error rate performance. This robust read channel system can be used for high-speed signal processing and LSIs using nanometer-scale semiconductor processes.

A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channel

A 0.13 /spl mu/m CMOS DVD SoC has been developed, reducing the die size from a previous 64 mm/sup 2/ to 34mm/sup 2/ without degrading its performance and functionality, by optimizing the chip architecture and implementation scheme in the same generation process technology. The presented SoC features a novel PRML read channel, employing full digital equalizers with an oversampling method to improve system stability while keeping channel quality.

Quasi-Synchronous Sampling and Adaptive Partial-Response Maximum-Likelihood Read-Channel System

We propose a read-channel system with quasi-synchronous sampling and an adaptive partial-response maximum-likelihood (PRML) method to achieve accurate timing recovery and correct data extraction under high-density recording with a high transfer rate. The proposed system can extract data correctly in the state of either oversampling or undersampling using first-in-first-out flip-flops (FIFOs) and an asynchronously sampled data processable maximum-likelihood detector (ASML). In other words, it allows a sampling clock to be incompletely synchronized with a channel bit. Furthermore, the ASML adaptively learns the references required for calculating branch metrics even though the input data are not synchronized with the channel bit. This system achieves stable data extraction under quasi-synchronous sampling, improves the bit-error-rate performance, and can be applied to next-generation, high-density, and high-transfer-rate storage systems.