M. Masahara

Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel

The FT-FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel have successfully been fabricated by using newly developed orientation-dependent wet etching. The flexible V/sub th/ controllability by using one of the double gates as a control gate and by the synchronized driving mode operation is experimentally confirmed. The developed processes are attractive for the fabrication of the advanced separate-gates FinFET for a flexible function VLSI circuit.

Characterization of metal-gate FinFET variability based on measurements and compact model analyses

A FinFET compact model, which provides physical representation of measurement data, was developed and was successfully applied to the characterization of sate-of-the-art metal-gate (MG) FinFETs. By combining the transistor size measurement and the model parameter calibration, the Vth variation of the MG FinFETs was analyzed into structure-based (TSi, LG) and material-based (gate work-function) variations for the first time. In addition, the extracted variations were incorporated into the compact model, and FinFET SRAM variability for hp-32-nm node was predicted.

Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform

Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very low off-currents (on the order of a few pA/μm) have been experimentally realized on the Si CMOS platform. Improvements in the SSs have been realized by optimizing epitaxial channel growth on heavily arsenic- and boron-doped source surfaces for purging interface defects at the epitaxial tunnel junctions. By improving the interface quality, SSs of 58 and 56 mV/decade and on/off current ratios (ON/OFF) of 2 × 106 and 3 × 104 (with VD = |0.2| V) were respectively obtained for p- and n- tunnel FETs (TFETs) simultaneously.

Lowest variability SOI FinFETs having multiple V t by back-biasing

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (V_t) necessary for multiple V_t solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (I_on) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of V_t (A_Vt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (G_m). Back-biasing through the SOTB provides excellent V_t controllability keeping the low V_t variability in contrast to V_t tuning by fin channel doping.

A Dynamical Power-Management Demonstration Using Four-Terminal Separated-Gate FinFETs

Dynamically power-controllable CMOS inverters have been successfully demonstrated using separated-gate four-terminal (4T) FinFETs. The threshold voltages of the both pMOS and nMOS FinFETs can be flexibly controlled by applying a bias voltage to the control-gate. We demonstrate for the first time that the power consumption of the CMOS inverter can be dynamically controlled using the variable threshold voltage provided by the 4T-FinFET. These results strongly suggest the advantage of the power-managed CMOS circuits using 4T-FinFETs

Advanced FinFET technology: TiN metal-gate CMOS and 3T/4T device integration

As advanced FinFET technologies, we have developed the co-integration techniques of the TiN gated high-performance 3T- and flexible V/sub th/ 4T-FinFETs. By using the conventional reactive sputtering of TiN, the well symmetrical V/sub th/ N- and P-channel 3T-FinFETs and the high V/sub th/-controllable 4T-FinFETs using the resist etch-back process have been demonstrated. The developed technologies are attractive to materialize the high-performance and power-managed FinFET CMOS circuits.

Impact of extension and source/drain resistance on FinFET performance

The parasitic resistance of the FinFET is investigated by the measurement based analysis. The R_S/D model suggests that careful optimization as to the NiSi incorporation is necessary for the effective R_p reduction. The R_ext seriously increases the R_p for T_finLt25 nm and also causes the R_p variability due to the T_fin variation.

Accurate prediction of PBTI lifetime for N-type fin-channel tunnel FETs

The positive bias temperature instability (PBTI) characteristics for n-type fin-channel tunnel FETs (TFETs) with high-k gate stacks have been thoroughly investigated and compared with conventional FinFETs. The subthreshold slope (SS) is not degraded at all while the threshold voltage (Vth) shifts in the positive direction by the PBTI stress. The activation energy of ΔVth for TFETs is almost the same as FinFETs, indicating that the PBTI mechanism for TFETs is almost the same as FinFETs. It was found that, by applying a positive bias to the n+-drain (normal operation condition), the PBTI lifetime is dramatically improved as compared with that in the conventional stress test (both the p+-source and n+-drain are grounded). This is because carrier injection from the n+-drain is the main cause of the PBTI, especially for n-type TFETs. Thus, the realistic impact of the PBTI is significantly mitigated for n-type TFETs.

First demonstration of drain current enhancement in SOI tunnel FET with vertical-tunnel-multiplication

CMOS tunnel FETs (TFETs) with vertical-tunnel-multiplication (VTM) were fabricated. VTM TFETs initiate band-to-band tunneling (BTBT) parallel to the gate electric field and effectively extend the tunnel area. Impact of the VTM was analyzed using a distributed-element circuit model, and the drain current multiplication by extended tunnel area was experimentally revealed for the first time.

Advanced FinFET process technology for 20 nm node and beyond

One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper presents novel FinFET process technologies for 20 nm node and beyond.