S. O'uchi

On the gate-stack origin threshold voltage variability in scaled FinFETs and multi-FinFETs

The Vt variability in scaled FinFETs with gate length (Lg) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., work-function variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching contribute to, not only the reduction of fin thickness (TSi) fluctuations, but also the reduction of gate-stack origin VTV. Moreover, it was experimentally found that the Vt of multi-FinFETs with the same gate area reduces with increasing the number of fins.

Experimental Evaluation of Effects of Channel Doping on Characteristics of FinFETs

We investigated channel doping in fin-type double-gate (DG) MOSFETs. We demonstrated through experiments that the threshold voltage was more sensitive to the dopants in the accumulation mode than in the inversion mode. We also found that significant deviation in the threshold voltage from the expected value arose in ultrathin fin-type DG MOSFETs. We attributed this phenomenon to the unexpected dopant loss from the ultrathin channels due to segregation. This finding means that careful doping adjustments must be made in ultrathin-channel devices.

Characterization of metal-gate FinFET variability based on measurements and compact model analyses

A FinFET compact model, which provides physical representation of measurement data, was developed and was successfully applied to the characterization of sate-of-the-art metal-gate (MG) FinFETs. By combining the transistor size measurement and the model parameter calibration, the Vth variation of the MG FinFETs was analyzed into structure-based (TSi, LG) and material-based (gate work-function) variations for the first time. In addition, the extracted variations were incorporated into the compact model, and FinFET SRAM variability for hp-32-nm node was predicted.

Advanced FinFET CMOS Technology: TiN-Gate, Fin-Height Control and Asymmetric Gate Insulator Thickness 4T-FinFETs

We have successfully developed the advanced FinFET fabrication processes for materializing FinFET CMOS circuits. Using the developed technologies, we demonstrate the advanced TiN metal gate, fin-height controlled FinFET CMOS inverter with an excellent transfer performance, and the flexible threshold voltage, asymmetric gate insulator thickness four-terminal (4T) FinFET with a greatly improved subthreshold (S) slope, for the first time

Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect

In this letter, we propose a synthetic electric field (SE) effect to enhance the performance of tunnel field-effect transistors (TFETs). The novel SE-TFET architecture utilizes both horizontal and vertical electric fields induced by a gate electrode that is wrapped around an ultrathin epitaxial channel. The drain current of the SE-TFET is increased up to 100 times in comparison with those of conventional TFETs. The subthreshold slope of the SE-TFET also improved, and enhanced to 52 mV/decade by scaling the channel width and channel thickness.

Fluctuation Analysis of Parasitic Resistance in FinFETs With Scaled Fin Thickness

Measurement-based analysis of the parasitic resistance (<i>R</i> _para) of FinFETs was extended to investigation of <i>R</i> _para fluctuation, which could cause severe on-current variation. <i>R</i> _para was obtained from the intercept in the linear relationship between measured on-resistance and gate length for FinFETs of various dimensions. A significant increase in <i>R</i> _para is observed for fin thickness below 25 nm due to dopant loss from the ultrathin extension during processing. <i>R</i> _para variation was evaluated for 45 FinFETs with an average fin thickness of 16 nm. Significant <i>R</i> _para variation is observed and correlates with the variation of fin thickness.

Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform

Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very low off-currents (on the order of a few pA/μm) have been experimentally realized on the Si CMOS platform. Improvements in the SSs have been realized by optimizing epitaxial channel growth on heavily arsenic- and boron-doped source surfaces for purging interface defects at the epitaxial tunnel junctions. By improving the interface quality, SSs of 58 and 56 mV/decade and on/off current ratios (ON/OFF) of 2 × 106 and 3 × 104 (with VD = |0.2| V) were respectively obtained for p- and n- tunnel FETs (TFETs) simultaneously.

Suppressing V t and G m variability of FinFETs using amorphous metal gates for 14 nm and beyond

Amorphous TaSiN metal gates (MGs) are successfully introduced in Fiwork function variationnFETs to suppress work function variation (WFV) of the MG, which is a dominant contributor to threshold voltage (Vt) variability of the undoped channel MG FinFETs. Comparing with a poly-crystalline TiN gate, the TaSiN gate reduces Vt variation drastically and records the smallest AVt value of 1.34 mVμm reported so far for MG FinFETs. Interface traps also become a dominant AVt origin in the case of well-suppressed WFV using the amorphous M G. The WFV suppression is also effective to reduce trans-conductance (Gm) variability which will be a dominant source of on-current (Ion) variability in 14 nm technology and beyond.

Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance

We compared the electrical characteristics, including mobility and on -state current <i>I</i>_on, of n⁺-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights <i>H</i>_fin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length <i>Lg</i> decreases, <i>I</i>_on for devices with tall fins becomes worse, probably due to a high parasitic resistance <i>Rp</i>. Furthermore, <i>V</i>_th variation increased with increasing <i>H</i>_fin due to rough etching of the fin sidewall. Process technologies for reducing <i>Rp</i> and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.

Variability Origins of Parasitic Resistance in FinFETs With Silicided Source/Drain

Origins of parasitic resistance <i>R</i>_para fluctuation were investigated by a measurement-based analysis for fin-shaped FETs (FinFETs) with NiSi in the source/drain (S/D). Fluctuation in the extension resistance <i>R</i>_ext reflecting fin thickness <i>T</i>_fin fluctuation is negligible for the sufficiently small thickness of the sidewall spacer. Although the NiSi incorporation in the S/D reduces <i>R</i>_para on average, it causes additional fluctuation of <i>R</i>_para. Analyzing the correlation of the <i>R</i>_para fluctuation with the fluctuation in <i>T</i>_fin and the lateral growth of NiSi, the dominant origin of the <i>R</i>_para fluctuation is specified to be the NiSi/n⁺-Si contact resistance.