Hisakazu Kotani

A 4-Mbit DRAM with 16-bit concurrent ECC

A 256 K-word*16-bit dynamic RAM with concurrent 16-bit error correction code (ECC) has been built in 0.8- mu m CMOS technology, with double-level metal and surrounding high-capacitance cell. The cell measures 10.12 mu m/sup 2/ with a 90-fF storage capacitance. A duplex bit-line architecture used on the DRAM provides multiple-bit operations and the potential of high-speed data processing for ASIC memories. The ECC checks concurrently 16-bit data and corrects a 1-bit data error. This ECC method can be adapted to higher-bit ECC without expanding the memory array. The ratio of ECC area to the whole chip is 7.5%. The cell structure and the architecture allow for expansion to 16-Mb DRAM. The 4-Mb DRAM has a 70-ns RAS access time without ECC and a 90-ns RAS access time with ECC. >

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

A 16-Mb dynamic RAM has been designed and fabricated using 0.5- mu m CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4*17.38 (93.85) mm/sup 2/ to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time. >

A 256-Mb DRAM with 100 MHz serial I/O ports for storage of moving pictures

A 256-Mb DRAM with refresh-free-FIFO function for storage of moving pictures has been developed using 0.25-/spl mu/m CMOS technology. An operating current of 73 mA (reduction of 52% compared with a conventional circuit) has been achieved at 100 MHz based on introducing (1) a suppressed High(H)-level differential data transfer scheme which ran be operated at 0.6 V, (2) a new pre-charge method which features a 1/2 VCC precharge level in read cycle and VSS pre-charge level in write cycle, and (3) a divided operation of array circuits for serial access. >

A proposed structure of a 4 Mbit content-addressable and sorting memory

A new structure for a high-density 4-Mb CAM (content addressable memory) with sorting function (sort-CAM) is proposed. Retrieval or sorting operations are done in word-parallel/bit-serial manner at the device. This is different from previous CAMs where operations are done in word-parallel/bit-parallel or flash manner. The device organization, circuits for retrieval or sorting, and chip operations are explained. Estimated performance of the device and chip size are also discussed. The device has 64 K-word×64-b organization and a 3.1-MB/s sorting speed. In practical applications, such as RDB (relational database) systems, this speed is enough, but a number of chips should be connected if larger data volume is needed

A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier

An 8-Mb (1-Mwords*8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7- mu m n-well CMOS, double-level polysilicon, single-polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell structure. The cell size is 1.8*3.0 mu m/sup 2/, and the chip area is 12.7*16.91 mm/sup 2/. >