Masaki Fujiu

A 70nm 16Gb 16-level-cell NAND Flash Memory

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same design rule. New programming method achieves 0.62 MB/s programming throughput.

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.

A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology

An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.

7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology

The demand for high-throughput NAND Flash memory systems for mobile applications such as smart phones, tablets, and laptop PCs with solid-state drives (SSDs) has been growing recently. To obtain higher throughput, systems employ multiple NAND Flash memories operating simultaneously in parallel. The available power for a mobile device is severely restricted and the peak total operating current may be high enough to cause large supply-voltage drop or even an unexpected system shutdown. Therefore it is important for NAND Flash memories to reduce operating power and peak operating current.

A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology

A 75 mm2 low power 64 Gb MLC NAND flash memory capable of 30 MB/s program throughput and 533 MB/s data transfer rate at 1.8 V supply voltage is developed in 15 nm CMOS technology. 36% power reduction from 3.3 V design is achieved by a new pumping scheme. New low current peak features reduce a multi-die concurrent programming peak by 65% for 4-die case, and an erase verifying peak by 40%, respectively. Nanoscale transistors reducing bit-line discharge time by 70% is introduced to improve performance.