Hiroshi Umeda

Two concerns about NBTI issue: gate dielectric scaling and increasing gate current

In order to obtain a clear perspective concerning the negative bias temperature instability (NBTI) issue toward 65-nm-node and beyond, (1) the impact of thinning gate dielectric on the basic mechanism of NBTI and (2) the influence of gate electron current on NBTI degradation rate have been investigated. Both were studied with focus on the hydrogen release reaction. This is believed to be the origin of NBTI. By studying the diffusion behavior of released hydrogen, we have clarified that our experimental results of NBTI degradation obtained under voltage-accelerated conditions can be explained by the widely accepted diffusion-controlled model without taking the influence of the gate electrode interface into account even in the case of sub-nm SiON gate dielectrics. However, from numerical calculations, it has been shown that the effect of the gate electrode interface on the diffusion behavior of released hydrogen should be taken care of at stress voltage as low as that of practical operation. In particular, the possibility of NBTI worsening due to thinning gate dielectric has been suggested especially for low stress voltage. To foresee this NBTI worsening and to evaluate NBTI lifetime precisely, we have proposed temperature-acceleration test instead of voltage-acceleration test. Next, by studying NBTI of n+gate-pMOSFET in which the influence of gate electron current is dramatically emphasized, it has been examined whether electron current flowing through gate dielectric will affect NBTI or not. Although the primary driving force of NBTI is considered to be the electric field, electron tunneling current that flows under NBT stress has been shown to worsen NBTI via the suppression of the reverse reaction of hydrogen release.

Universality of power-law voltage dependence for TDDB lifetime in thin gate oxide PMOSFETs

Voltage, polarity and thickness dependencies of time-to breakdown in n-FETs and p-FETs are investigated under inversion and accumulation conditions. The voltage dependence of all the cases is clearly described by a power-law. The voltage acceleration exponents (n) of the power-law of 45 (n-FETs inv.), 40 (n-FETs acc.) and 44 (p-FETs acc.) are independent of thickness. On the other hand, in p-FETs under inversion mode, the exponents (n) are /spl sim/45 for |Vg|>3.8 V and 33 for |Vg|<3.8 V, regardless of thickness. This change in the exponent (n) is explained by a cathode side hydrogen release model.

A simple approach to optimizing ultra-thin SiON gate dielectrics independently for n- and p-MOSFETs

A technique for optimizing ultra-thin (EOT ~ 1.1-1.3 nm) SiON gate dielectrics independently for n- and p-MOSFETs is demonstrated. Selective nitrogen-enrichment for the nMOS and fluorine incorporation to the pMOS regions were both performed by ion implantation into the Si-substrate with resist masks before gate oxidation. The former provided suppression of gate leakage current and enhancement of drain current to nMOSFETs. The latter improved the NBTI of pMOSFETs without enhancing the B penetration. Moreover, the incorporation of F was found to be a quite useful tool for lowering |Vth| in pMOSFETs. The incorporation of F was shown to bring down pMOS |Vth| by more than 150 mV without any degradation in hole mobility or short channel effect immunity. Since pMOSFETs with N-rich SiON gate dielectrics, as well as high-k pMOS, suffer from excessively high |Vth|, this finding is quite important. In fact, by applying the F-incorporation technique to 65-nm devices, significant Ion enhancement (~8%) was successfully achieved for high Ioff conditions. This technique is considered operative also for pMOSFETs with high-k gate dielectrics and/or metal gate electrodes

Control of nitrogen depth profile near silicon oxynitride/Si(100) interface formed by radical nitridation

Depth profiles of composition and chemical structures in radical nitrided silicon oxynitride films formed with Ar/N2, Xe/N2, or Ar/NH3 plasma excited by microwave have been investigated by X-ray photoelectron spectroscopy combined with step etching in HF solution. The relationship between the intensities of emission from N2+ radical in these plasmas and the concentration of nitrogen atoms forming Si3≡N configuration near the silicon oxynitride film/Si substrate interface nitrided using these plasmas was studied. The emission intensities from N2+ radical generated in Xe/N2 or Ar/NH3 plasma are a quarter or one-sixth of that from N2+ radical generated in Ar/N2 plasma respectively. However, the emission from NH radical is also detected in Ar/NH3 plasma. Although the nitrogen concentration of Xe/N2 plasma is smaller than that of Ar/N2 plasma at the film/substrate interface, that of Ar/NH3 plasma is larger than that of Ar/N2 plasma at the interface. It is important for the reduction of the nitrogen concentration near the film/substrate interface to use Xe/N2 plasma in which both of the generation efficiencies of N2+ and NH radicals are low.

Control of Nitrogen Depth Profile and Chemical Bonding State in Silicon Oxynitride Films Formed by Radical Nitridation

Chemical bonding states and depth profiles of nitrogen in radical nitrided silicon oxide film formed in Ar/N2 plasma excited by microwave has been investigated using X-ray photoelectron spectroscopy with HF step etching. The main chemical bonding state of nitrogen atom is Si3≡N configuration, and the other unknown bonding state (termed Nhigh) is observed, whose peak energy shift is about +4.8 eV. The nitrogen atoms forming Si3≡N configuration accumulate only at the film surface and those forming Nhigh configuration are distributed deeper in the films. The Nhigh bond is very weak because it is desorbed completely at low temperature (300–500°C). Although the nitrogen atoms forming Nhigh configuration are removed by post O2-annealing, those forming Si3≡N configuration migrate toward the film/substrate interface and they increase negative bias temperature instability. In the case of ultra thin film, nitriding species forming Nhigh bond reach the film/substrate interface and form Si3≡N bond at the interface. Suppression of the generation of nitriding species forming Nhigh bond in the plasma is very important. It is clear that Nhigh bond is reduced using Ar/NH3 plasma.

V/sub ox//E/sub ox/-driven breakdown of ultra-thin SiON gate dielectric in p+gate-pMOSFET under low stress voltage of inversion mode

We have studied the breakdown mechanism of ultra-thin SiON gate dielectrics in p+gate-pMOSFETs. A systematic study with varying gate doping concentrations has revealed that, in the case of p+gate-pMOSFETs in inversion mode, gate dielectric breakdown under low stress voltage is driven by oxide voltage (V/sub ox/) or oxide field (E/sub ox/), while the breakdown under higher stress voltage is driven by gate voltage (V/sub g/). The V/sub ox//E/sub ox/-driven breakdown which emerges under low stress voltage is quite important to the reliability of low-voltage CMOS. By studying the mechanism of the breakdown, it has been clarified that the breakdown is not induced by electron current. The concept that the breakdown is due to the same mechanism as NBTI, namely the interfacial hydrogen release driven by E/sub ox/, has been shown to be possible. However, direct tunneling of holes driven by V/sub ox/ has also been found to be a possible driving force of the breakdown. Although a decisive conclusion concerning the mechanism issue has not yet been obtained, the key factor that governs the breakdown has been shown to be V/sub ox/ or E/sub ox/.

SiN Gate Dielectric with Oxygen-enriched Interface (OI-SiN) Utilizing Dual-core-SiON Technique for hp65-SoC LOP Application

A solution of utilizing an N-rich SiON gate dielectric toward achieving highly reliable pMOS is demonstrated. The solution consists of a combination of two techniques: (1) a SiN-based gate dielectric with oxygen-enriched interface (OI-SiN) enabling nMOS and pMOS characteristics superior to plasma-nitrided oxides (PNO) and (2) a dual-core-SiON technique in which SiON in pMOS is selectively thickened by fluorine ion implantation to the poly-Si layer with the aim of acquiring NBTI immunity. The latter improved the NBTI immunity of pMOS with OI-SiN gate dielectrics to a level comparable to that with conventional PNO. Although the thickening of SiON using dual-core-SiON technique naturally decreases pMOS on-current, the performance remains superior to that with PNO

The Progress in Ultra Thin Gate Dielecgtric for System LSI Application

EOT reduction is a key challenge to keep the Moores law, especially in low power LSIs. Nice candidates of gate dielectric as alternative to conventional SiO2 are N-rich SiON and high-K. However, in each case, we truly need tuning tools of Vth in the system LSI applications. F incorporation technique should be effective in Vth tuning with both N-rich SiON and high-K. Moreover, F incorporation is promising from reliability aspect