Shimpei Tsujikawa

Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics

The negative bias temperature instability (NBTI) of pMOSFETs with ultra-thin gate dielectrics was investigated from four points of view: basic mechanism of NBTI, dependence of NBTI on gate dielectric thickness, mechanism of NBTI enhancement caused by addition of nitrogen to the gate dielectrics, and possibility of applying SiON gate dielectrics with a high concentration of nitrogen. By investigating the behavior of FET characteristics after NBT stresses were stopped, it was clarified that a portion (60%, in our case) of hydrogen atoms released by the NBT stress remains in the gate dielectric in the case of a 1.85-nm-thick NO-oxynitride gate dielectric. The existence of the hydrogen was shown to lead to the generation of positive fixed charges in the gate dielectric. It was also found that NBTI depends little on gate dielectric thickness. Moreover, we revealed that the origin of NBTI enhancement by incorporating nitrogen into gate dielectrics is the property of attracting H/sub 2/O or OH. We speculate that this property is due to the existence of positive fixed charges induced by undesirable nitrogen. We evaluated NBTI immunity of SiN gate dielectrics with an oxygen-enriched interface (OI-SiN) in which high carrier mobility was obtained by reducing positive fixed charges. OI-SiN gate dielectrics with EOTs of 1.4 and 1.6 nm were found to have sufficient lifetime for practical use under 1 V operation.

Effects of remote-surface-roughness scattering on carrier mobility in field-effect-transistors with ultrathin gate dielectrics

We examined effects of the remote surface roughness, which is the roughness between the polycrystalline silicon gate and gate dielectric, on the inversion carrier mobility of metal-insulator-semiconductor field-effect-transistors with ultrathin gate dielectrics. We calculated the effective mobility by the linear response theory and found that the scattering from the remote surface roughness reduces the effective mobility especially at high vertical fields. The effective mobility is severely reduced, if the correlation length of the remote surface roughness is comparable to the inverse of thermal de Broglie wave number. We show that the hole mobility reduction experimentally found for the transistor with the Al2O3 gate dielectric can be explained by this scattering.

Experimental evidence for the generation of bulk traps by negative bias temperature stress and their impact on the integrity of direct-tunneling gate dielectrics

Negative Bias Temperature Instability (NBTI) of pMOSFETs with direct-tunneling gate dielectrics was studied in detail. By investigating the effects of positive bias stress on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBT stress was clearly demonstrated for the first time. We consider that the bulk trap generation is due to hydrogen atoms released from the interface. Moreover, we investigated the impact of the bulk traps on the SILC and TDDB, and described strong indications that the same mechanism, namely the hydrogen release, is responsible for both NBTI and TDDB of pMOSFETs.

Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface

We demonstrate 40-nm CMOS transistors for the 70-nm technology node. This transistor uses a high-k offset spacer (EOS: high-epsilon offset spacer) in achieving both a short-channel and high drivability along with SiN gate dielectrics with oxygen-enriched interface (OI-SiN) to suppress both the gate-leakage current and boron penetration. Consequently, N-MOSFET and P-MOSFET have high drive currents of 0.68 and 0.30 mA//spl mu/m, respectively, with I/sub off/=10 nA//spl mu/m, with an EOT value of 1.4 nm. The record gate delay of 280 fs (3.6 THz), for an N-MOSFET with the gate length of 19 nm, has also been achieved.

An ultra-thin silicon nitride gate dielectric with oxygen-enriched interface (OI-SiN) for CMOS with EOT of 0.9 nm and beyond

We demonstrate a SiN gate dielectric with oxygen-enriched interface (OI-SiN). A process in which oxygen atoms are incorporated after forming SiN provides enhanced nitrogen concentration and oxygen-enriched interface simultaneously even in the region of EOT < 1.5 nm. Thus we developed an OI-SiN gate dielectric with EOT of 0.9 nm that brought about low gate leakage current, good interface properties and excellent resistance to boron penetration.

Vox/Eox-Driven Breakdown of Ultrathin SiON Gate Dielectrics in p-Type Metal Oxide Semiconductor Field Effect Transistors under Low-Voltage Inversion Stress

The breakdown mechanism of ultrathin SiON gate dielectrics in p-type metal oxide semiconductor field effect transistors having p+gates (p+gate-pMOSFETs) has been studied. Systematic study with varying gate doping concentrations has revealed that, in the case of p+gate-pMOSFET in inversion mode, gate dielectric breakdown under stress voltage lower than � 4 V is driven by oxide voltage (Vox) or oxide field (Eox), while the breakdown under stress voltage higher than � 4 Vi s driven by gate voltage (Vg). The Vox=Eox-driven breakdown observed under low stress voltage is quite important to the reliability of low-voltage complementary metal oxide semiconductor (CMOS). By studying the mechanism of the breakdown, it has been clarified that the breakdown is not induced by electron current. The concept that the breakdown is due to same mechanism as the negative bias temperature instability (NBTI), namely the interfacial hydrogen release driven by Eox, has been shown to be possible. However, direct tunneling of holes driven by Vox has also been found to be a possible driving force of the breakdown. Although a decisive conclusion concerning the mechanism issue has not yet been obtained, the key factor that governs the breakdown has been shown to be Vox or Eox. [DOI: 10.1143/JJAP.46.7]

Control of nitrogen profile in radical nitridation of SiO2 films.

Advanced Technology R&D Center, Mitsubishi Electric Corporation, 8-1-1, Tsukaguchi-Honmachi, Amagasaki, Hyogo 661-8661, Japan. Phone: +81-6-6497-7545 E-mail: kawase.kazumasa@wrc.melco.co.jp Process Development Dept., Wafer Process Engineering Development Div., LSI Manufacturing Unit, Renesas Technology Corporation, 4-1, Mizuhara, Itami, Hyogo 664-0005, Japan. 3 Department of Electronic Engineering, Graduate School of Engineering, Tohoku Univ., Aoba, Aramaki, Aoba-ku, Sendai, Miyagi 980-8579, Japan. New Industry Creation Hatchery Center, Tohoku Univ., Aoba, Aramaki, Aoba-ku, Sendai, Miyagi 980-8579, Japan.

Impact of oxygen-enriched SiN interface on Al/sub 2/O/sub 3/ gate stack. An innovative solution to low-power CMOS

A SiN dielectric with oxygen-enriched interface (OI-SiN) was applied as an interfacial layer of an Al/sub 2/O/sub 3/ stack. The OI-SiN interface, where the nitrogen profile is controlled and the fixed charge is suppressed, can solve critical issues for high-/spl kappa/ dielectrics; impurity penetration through conventional processes, and reduced mobility due to Coulomb scattering. Thus, the drivability with low-leakage current is ensured. We show a scaling strategy to integrate the OI-SiN/Al/sub 2/O/sub 3/ stack which is suitable for low-power applications.

High-κ /Oxynitride Gate Dielectric - Searching for Serendipitous Materials -

The development of high-κ gate stacks, in which the gate length is less than 50 nm and the thickness is only a few nanometers, is the cutting-edge of material science and nanotechnology. It is particularly critical to integrate transition metal oxides (which need a high-temperature oxidation process) into sophisticated high-density devices. This is because a DRAM capacitor dielectric of Ta2O5 is the only successful application of the metal oxide in the past two decades with the exception of low-density FeRAMs. In this paper, we discuss the approach to developing high-κ gate materials.