Hirotaka Ichikawa

Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control

Although Self-Aligned Double and Quadruple Patterning (SADP, SAQP) have become the most promising processes for sub-20 nm and sub-14 nm node advanced technologies, not all wafer images are realized by them. In advanced technologies, feasible wafer images should be generated effectively by utilizing SADP and SAQP where a wafer image is uniquely determined by a selected mandrel pattern. However, predicting the wafer image of a mandrel pattern is not easy. In this paper, we propose a routing method of generating a feasible wafer image satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SADP) or three colors (SAQP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, hotspot reduction by dummy pattern flipping is proposed. In experiments, feasible wafer images meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed.

Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods

Although self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all layouts are compatible with them. In advanced technologies, feasible wafer image should be generated effectively by utilizing SADP and SAQP where a wafer image is determined by a selected mandrel pattern. However, predicting a mandrel pattern is not easy since it is different from the wafer image (or target pattern). In this paper, we propose new routing methods for spacer-is-dielectric (SID)-type SADP, SID-type SAQP, and spacer-is-metal (SIM)-type SADP to generate a feasible layout satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SID-type SADP) or three colors (SID-type SAQP and SIM-type SADP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, we try to reduce hotspots (potentially defective regions) by the proposed dummy pattern flipping for SID-type SADP. In experiments, feasible layouts meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed.

Detailed routing with advanced flexibility and in compliance with self-aligned double patterning constraints

In this paper, we propose a new flexible routing method for Self-Aligned Double Patterning (SADP). SADP is one of the most promising candidates for patterning sub-20 nm node advanced technology but wafer images must satisfy tighter constraints than litho-etch-litho-etch process. Previous SADP routing methods require strict constraints induced from the relation between mandrel and trim patterns, so design freedom is unexpectedly lost. Also these methods assume to form narrow patterns by trimming process without consideration of resolution limit of optical lithography. The proposed method realizes flexible SADP routing with dynamic coloring requiring no decomposition to extract mandrel patterns and no worries about coloring conflicts. The proposed method uses realizable trimming process only for insulation of patterns. The effectiveness of the proposed method is confirmed in the experimental comparisons.

Self-aligned quadruple patterning-aware routing

Self-Aligned Quadruple Patterning (SAQP) is one of the most leading techniques in 14 nm node and beyond. However, the construction of feasible layout configurations must follow stricter constraints than in LELELE triple patterning process. Some SAQP layout decomposition methods were recently proposed. However, due to strict constraints required for feasible SAQP layout, the decomposition strategy considering an arbitrary layout does not seem realistic. In this paper, we propose a new routing method for feasible SAQP layout requiring no decomposition. Our method performs detailed routing by correct-by-construction approach and offers compliant layout configuration without any pitch conflict.

Lithography simulation system for total CD control from design to manufacturing

Systematic design for manufacturability ( DfM ) scheme including triple gates for hot spot elimination under the low-k1 lithography condition is proposed and efficient approaches to the hot spot elimination at each development stage in the DfM scheme are discussed in view of the actual situation under the concurrent development of design rule ( DR ), layout, process, optical proximity correction ( OPC ) and resolution enhancement technique ( RET ) technologies. Integrated-type lithography simulation system with OPC tool is much available for the fast processing at the initial stage and promising to be complementarily used for the verification of chip-level layout with conventional-type one at the final development stage. Low order of the lithography empirical model originating moderate prediction accuracy for all kinds of patterns is hopeful to be used at the initial development stage because it is difficult to obtain a lot of reliable experimental data for making the accurate empirical lithography model due to frequent improvement of the process, OPC and RET technologies. At the final development stage, sufficient and reliable experimental data for device pattern variations allow us to implement the higher order of the empirical model. The DfM scheme with efficient approaches in view of the actual situation under the concurrent development is found to be promising for the robust pattern formation under the low-k1 lithography condition.

Efficient hybrid optical proximity correction method based on the flow of design for manufacturability (DFM)

Design and optical proximity correction (OPC) flow with hybrid OPC and manufacturability check (MC) tool was found to be effective for making robust pattern formation without any hot spots within feasible lead time under the low-k1 lithography condition. MC at design stage is essential for cleaning up hot spots in three ways; the refinement of design rule, the guideline for repairing hot spots for designers and the refinement of OPC deck. Hybrid OPC and MC tools with library- and model-based modules are available for reducing lead time by taking advantage of library system. Due to the design and OPC flow with the library-based OPC and MC tool, total lead time can be reduced to 55% of that in the case of conventional flow with MC. Assuming that a refined mask is ordered due to issue of hot spots without MC, the total lead time in the new flow can be reduced to 11% of that in the case of conventional technology.

Advanced hybrid optical proximity correction system with OPC segment library and model-based correction module

Advanced hybrid optical proximity correction (OPC) system with OPC segment library and a model-based correction module has been found to be much promising for reducing the mask data processing time. Recycling the OPC segment library made of previous products for next derivative products with common design rule could reduce the OPC process time down to 11% at the sixth Application Specific Integrated Circuit product for the conventional hybrid OPC scheme. Then, under the circumstances that the block-level layout verification tool with the hybrid OPC tool and the lithography simulator is utilized by designers for avoiding the lithographic dangers in the early stage of design, the most effective library can be generated in this layout verification flow and used for the correction of the completed layout. Due to this scheme, the OPC process time could be decreased to 11-16% for 256-Mbit Dynamic Random Access Memory gate and metal layer.

Hotspot detection using image pattern recognition based on higher-order local auto-correlation

Below 40nm design node, systematic variation due to lithography must be taken into consideration during the early stage of design. So far, litho-aware design using lithography simulation models has been widely applied to assure that designs are printed on silicon without any error. However, the lithography simulation approach is very time consuming, and under time-to-market pressure, repetitive redesign by this approach may result in the missing of the market window. This paper proposes a fast hotspot detection support method by flexible and intelligent vision system image pattern recognition based on Higher-Order Local Autocorrelation. Our method learns the geometrical properties of the given design data without any defects as normal patterns, and automatically detects the design patterns with hotspots from the test data as abnormal patterns. The Higher-Order Local Autocorrelation method can extract features from the graphic image of design pattern, and computational cost of the extraction is constant regardless of the number of design pattern polygons. This approach can reduce turnaround time (TAT) dramatically only on 1CPU, compared with the conventional simulation-based approach, and by distributed processing, this has proven to deliver linear scalability with each additional CPU.