Shoji Mimotogi

Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control

Although Self-Aligned Double and Quadruple Patterning (SADP, SAQP) have become the most promising processes for sub-20 nm and sub-14 nm node advanced technologies, not all wafer images are realized by them. In advanced technologies, feasible wafer images should be generated effectively by utilizing SADP and SAQP where a wafer image is uniquely determined by a selected mandrel pattern. However, predicting the wafer image of a mandrel pattern is not easy. In this paper, we propose a routing method of generating a feasible wafer image satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SADP) or three colors (SAQP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, hotspot reduction by dummy pattern flipping is proposed. In experiments, feasible wafer images meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed.

Contact hole formation by multiple exposure technique in ultralow k 1 lithography

The double line and space (L&S) formation method with L&S masks and dipole illumination was found to have high capability to fabricate ~0.3 k1 contact hole (C/H) pattern. The procedure was as follows. The first L&S pattern was formed and was hardened to avoid the dissolution and mixing during the second resist coating. The second L&S pattern perpendicular to the first one was formed on the first resist pattern. The common space area of the two patterns became 1:1 C/H pattern. Simulation results showed that the double L&S formation method has much wider lithography latitude than other methods, such as single exposure of a C/H mask with quadrupole illumination, single exposure of a vortex mask with conventional illumination, and double exposure of L&S masks with dipole illumination to a single-layer resist. A 75 nm (0.30 k1) 1:1 C/H pattern was fabricated. An 80 nm (0.32 k1) 1:1 C/H pattern had 280 and 600 nm depth of focus in each resist layer at 8% exposure latitude. Moreover, a new method, in which a C/H mask replaces the L&S masks, is proposed to achieve cost reduction and the same high performance as the L&S masks.

Resist edge roughness with reducing pattern size

Recently, resist edge roughness with reducing pattern size has become a serious problem. We investigated the roughness of chemically amplified, positive-tone resists, experimentally. To reduce the roughness, we added a quencher with strong basicity to the resist, and observed sub quarter micron nested lines. As a result, the roughness was improved with increasing the quencher concentration, especially in 0.15 micrometers nested line patterns. Adding quencher was not too much effective for the larger size patterns. The acid concentration in resist was increased by adding quencher, because the nominal dose became large by that. It was also indicated experimentally that generated acid concentration at pattern edge was nearly equal to that of quencher at nominal dose. The nominal dose was determined by quencher concentration. We defined effective acid concentration as remaining acid concentration after quenching. This effective acid concentration increased with increasing quencher concentration too. The roughness seemed to be generated when effective acid concentration profile was lowered. It is indicated that the resist edge roughness with reducing pattern size can be expected from its effective acid concentration profile.

Novel error mode analysis method for graphoepitaxial directed self-assembly lithography based on the dissipative particle dynamics method

Directed self-assembly lithography (DSAL), which combines self-assembling materials and a lithographically defined prepattern, is a potential candidate to extend optical lithography beyond 22 nm. To take full advantage of DSAL requires diminishing not only systematic error modes but also random error modes by carefully designing a lithographically defined prepattern and precisely adjusting process conditions. To accomplish this with satisfactory accuracy, we have proposed a novel method to evaluate DSAL error modes based on simulations using dissipative particle dynamics (DPD). We have found that we can estimate not only systematic errors but also random errors qualitatively by simulations.

Detailed routing with advanced flexibility and in compliance with self-aligned double patterning constraints

In this paper, we propose a new flexible routing method for Self-Aligned Double Patterning (SADP). SADP is one of the most promising candidates for patterning sub-20 nm node advanced technology but wafer images must satisfy tighter constraints than litho-etch-litho-etch process. Previous SADP routing methods require strict constraints induced from the relation between mandrel and trim patterns, so design freedom is unexpectedly lost. Also these methods assume to form narrow patterns by trimming process without consideration of resolution limit of optical lithography. The proposed method realizes flexible SADP routing with dynamic coloring requiring no decomposition to extract mandrel patterns and no worries about coloring conflicts. The proposed method uses realizable trimming process only for insulation of patterns. The effectiveness of the proposed method is confirmed in the experimental comparisons.

Flexible mask specifications

As feature sizes of semiconductor devices shrink, mask errors have a large impact on critical dimension (CD) variation on a wafer and lead to lithography margin reduction. Observed CD error on a wafer is 2 to 4 times as large as CD error on a mask under the low k1 lithography due to mask CD deviation enhancement factor. Mask errors, e.g. CD uniformity, mean to target error, should be controlled and assessed to prevent CD variation on a wafer and lithography margin reduction. Therefore, assessment of mask quality is a critical step in mask manufacturing. This paper proposes a methodology for assessment of mask quality, flexible mask specifications. The methodology consists of two major concepts. One is flexibly selected patterns to guarantee mask quality for each device and each level of devices using full-chip level lithography simulation. The other is flexibly changeable combination of each tolerance for each error component. The validity of flexible mask specifications is proved on masks of a 130nm node memory device. Using the flexible mask specifications, we have confirmed that mask-manufacturing yield rises by 20% for masks of a 175nm node memory device compared with the yield of the masks judged by conventional mask specifications.

Optimization of directed self-assembly hole shrink process with simplified model

Abstract. Application of the directed self-assembly of block copolymer to the hole shrink process has gained large attention because of the low cost and high potential for sublithographic patterning. In this study, we have employed a simplified model, called the Ohta-Kawasaki model to find the optimal process conditions, which minimize the morphological defects of the diblock copolymer, PS-b-PMMA. The model parameters were calibrated with cross-sectional transmission electron microscopy images. Our simulation results revealed that it is difficult to eliminate the morphological defects (i.e., PS residual layer) by only varying the shape of the guide hole. It turned out that changing the affinity of the bottom surface of the guide hole from “PMMA attractive” to “neutral” is a more effective way to obtain a reasonably wide, defect-free process window. Note that our simulations are not only computationally inexpensive, but are also comparable to the other detailed models such as the self-consistent field theory; they may also be feasible for large-scale simulations such as the hotspot analysis over a large area.

Hotspot prevention and detection method using an image-recognition technique based on higher-order local autocorrelation

Abstract. Although a number of factors relating to lithography and material stacking have been investigated to realize hotspot-free wafer images, hotspots are often still found on wafers. For the 22-nm technology node and beyond, the detection and repair of hotspots with lithography simulation models is extremely time-consuming. Thus, hotspots represent a critical problem that not only causes delays to process development but also represents lost business opportunities. In order to solve the time-consumption problem of hotspots, this paper proposes a new method of hotspot prevention and detection using an image recognition technique based on higher-order local autocorrelation, which is adopted to extract geometrical features from a layout pattern. To prevent hotspots, our method can generate proper verification patterns to cover the pattern variations within a chip layout to optimize the lithography conditions. Moreover, our method can realize fast hotspot detection without lithography simulation models. Obtained experimental results for hotspot prevention indicated excellent performance in terms of the similarity between generated proposed patterns and the original chip layout patterns, both geometrically and optically. Moreover, the proposed hotspot detection method could achieve turn-around time reductions of >95% for just one CPU, compared to the conventional simulation-based approach, without accuracy losses.

Patterning strategy and performance of 1.3NA tool for 32nm node lithography

We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.

Impact of polarization on an attenuated phase shift mask with ArF hyper-numerical aperture lithography

In recent low-k1 lithography, the size of a mask pattern is becoming close to the wavelength of the light source. In a sub-100-nm pattern at wafer scale of 4× masks, transverse electric (TE) polarization light had higher transmittance of the zeroth order than TM polarization for a Cr mask according to rigorous model simulation of a finite difference time domain method. On the other hand, transverse magnetic (TM) polarization light had higher transmittance than TE polarization light for a MoSi mask. From the results of lithography simulation for a 45-nm pattern on the MoSi mask, TE polarization was better for wide exposure latitude, but TM polarization was better for large depth of field. The performance of a current MoSi mask is inferior to that of a Cr mask. However, a lower transmittance MoSi mask has better performance in the exposure defocus window under the dipole illumination. Also, rigorous simulation showed transmittance dependency of the light incident angle to the MoSi mask. The dependency was larger for TM polarization than for TE polarization.