Hiroto Kagotani

Asynchronous PipeRench: architecture and performance evaluations

PipeRench is a configurable architecture that has the unique ability to virtualize an application using dynamic reconfiguration. This paper investigates the potential benefits and costs of implementing this architecture using an asynchronous methodology. Since clock distribution and gating are relatively easy in the synchronous PipeRench, we focus on the benefit due to decreased timing pessimism in an asynchronous implementation. Two architectures for fully asynchronous implementation are considered. PE-based asynchronous implementation yields approximately 80% improvement in performance per stripe. This implementation, however, requires significant increases in configuration storage and wire count. A few particular features of the architecture, such as the crossbar interconnect structure within the stripe, are primarily responsible for this growth in configuration bits and wires. These features, however, are the primary aspects of the PipeRench architecture that make it a good compilation target.

Investigation in burst pulse injection method for fault based cryptanalysis

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs

We propose a method of synthesizing pipeline controllers as four-phase asynchronous circuits from specifications described as two-phase dependency graphs. Pipeline two-phase dependency graphs are transformed into four-phase ones by applying a transformation rule to each simple loop in the graphs. Four-phase dependency graphs are easily mapped onto four-phase asynchronous control circuits. We also discuss some simplification of four-phase dependency graphs.

A method of affine transformation for rectangular video image

This paper proposes the 1-affine transformation for rectangular video images. In the proposed method, each frame of the input rectangular video images is partitioned into small square subimages, which are stored separately in memory. Then, by applying the 90° rotation and the one-dimensional geometrical transformations alternately for two times each, the affine transformation is realized. The affine transformer based on this principle is realized by two kinds of functional modules corresponding to the 90° rotation and the one-dimensional geometrical transformation, respectively. The block diagram for the affine transformation is shown combining those functional modules. Calculation of the adequate size for the subimage, as well as the reduction of the memory speed requirement by the partitioning, are discussed. The proposed method can easily be applied to video images with different sizes only by modifying the combination of the two kinds of functional modules.