Hiroyuki Morinaga

Development of a Platform for Collaborative Engineering Data Flow between Design and Manufacturing

The amount of collaborative engineering data between design and manufacturing is increasing because of the introduction of design for manufacturing (DFM) technology to improve product yield quickly. Therefore, we developed a platform to realize collaborative engineering data flows between design and manufacturing. The platform can facilitate the implementation of flows of yield ramp-up and quick turn-around-time (TAT). The flows can reduce the TA T of information linkage. The flows which improve yield and manufacturability were established on the platform and integrated into the actual LSI production. As a result, we confirmed the improvement of efficiency of the system development and the TAT reduction of information linkage.

Mask defect specification in the spacer patterning process by using a fail-bit-map analysis

We obtained the acceptable mask defect size for both opaque and clear defects in the spacer patterning process using the fail-bit-map analysis and a mask with programmed defects. The spacer patterning process consists of the development of photoresist film, the etching of the core film using the photoresist pattern as the etching mask, the deposition of a spacer film on both sides of the core film pattern, and the removal of the core film. The pattern pitch of the spacer film becomes half that of the photoresist. Both the opaque defect and the clear defect of the mask resulted in a short defect in the spacer pattern. From the fail-bit-map analysis, the acceptable mask defect size for opaque and clear defects was found to be 80nm and 120nm, respectively, which could be relaxed from that in ITRS2008. The difference of the acceptable mask defect size for opaque and clear defects comes from the difference of the defect printability at the resist development.

Mask defect specifications with fail-bit-map analysis

A new mask methodology of mask defect specifications by fail-bit-map (FBM) analysis of LSI devices was proposed. In this paper, concept of new mask defect specifications based on the FBM analysis is shown and impacts on LSI devices of mask defects are studied and the new methodology for next generation is applied. The new mask defect specifications were implemented in a gate-level mask with defects programmed into a 0.175μm-rule DRAM fabrication process, as follows, Firstly, the programmed defects varied in terms of the types, locations and sizes were designed into the memory cell area on the 0.175μm-rule DRAM gate-level mask. Secondly, the gate-level mask with programmed defects was fabricated with conventional mask process flow and the actual mask defect sizes were measured. Thirdly, exposures of the gate-level mask were carried out with conventional 0.175μm-rule DRAM process. Finally, the large impacts on CDs caused by mask defect printability on wafers were clarified and FBM analysis was performed to characterize the relationship among the actual mask defect variations, the CD variations and electrical function of 0.175μm-rule DRAM. This relationship can facilitate determination of the mask defect specifications on 0.175μm-rule DRAM and also likely contribute to estimate next-generation defect specifications. According to the results of the above procedure, the mask defect specifications for opaque defects should be generally tighter than those for clear defects in view of the printability on the wafers and the FBM analysis. Nevertheless, the FBM results suggested that current mask inspection sensitivity for clear defects was too high. With the new methodology, in regard to the impacts of mask defects not only on wafer CDs but also on LSI devices, we have succeeded in obtaining useful results for the mask defect specifications.