Yasuhiro Kaga

Defect criticality index (DCI): a new methodology to significantly improve DOI sampling rate in a 45nm production environment

Increasing inspection sensitivity may be necessary for capturing the smaller defects of interest (DOI) dictated by reduced minimum design features. Unfortunately, higher inspection sensitivity can result in a greater percentage of non-DOI or nuisance defect types during inline monitoring in a mass production environment. Due to the time and effort required, review sampling is usually limited to 50 to 100 defects per wafer. Determining how to select and identify critical defect types under very low sampling rate conditions, so that more yield-relevant defect Paretos can be created after SEM review, has become very important. By associating GDS clip (design layout) information with every defect, and including defect attributes such as size and brightness, a new methodology called Defect Criticality Index (DCI) has demonstrated improved DOI sampling rates.

Development of Sample Planning for Wafer Defect Inspection

Sample planning for wafer defect inspection is a critical issue for reducing total cost. It is important to develop a cost‐effective sampling plan. In the present study, using three parameters (gain, coefficient of gain variation, and payback period), an optimized sampling plan has been identified by principal component analysis. In particular, a robust sampling plan can be evaluated in terms of a coefficient of gain variation and a cost‐effective sampling plan can be evaluated in terms of both gain and the payback period. This indicates that the optimal sampling plan must be designed from both economic and technical viewpoints to reduce the total inspection cost.