Miyoshi Saito

Technique for controlling effective Vth in multi-Gbit DRAM sense amplifier

We propose the use of a capacitor couple structure to control the effective threshold voltage (Vth) and its application to Vth fluctuation compensation in flip-flop sense amplifiers for multi-gigabit DRAMs. Our proposed sense amplifier functions correctly at up to a 500 mV fluctuation in Vth for the transistor pair in the latch. It does not require extra charging time in the sensing operation for compensation. In addition, the sense-amplifier speed is independent of the Vth value, so our S/A can also compensate the sensing speed fluctuation. This Vth control method and Vth-compensated sense amplifier opens up the possibility of utilizing transistors with gate lengths of less than 0.1 /spl mu/m, where the Vth variations could not be reduced.

Cluster architecture for reconfigurable signal processing engine for wireless communication

We describe a dynamic reconfigurable baseband signal-processing engine suitable for mobile communications that require short operation latency. Signals are processed using a cluster group, which consists of clusters containing heterogenous processor elements (PEs), inter-PE networks, and a sequencer that controls dynamic reconfiguration. The cluster group also has dedicated shared signal processing resources. In the cluster, combined data transfer and operations are carried out within one cycle to minimize operation latency, except for the multicycled PE. We evaluated the architecture by mapping several physical-layer IEEE802.11a and 11b wireless LAN algorithms. The results confirmed a shorter processing latency.

Electron waves through quantum point contacts

This paper reviews the authors work on the experimental and theoretical analyses of the angular distribution of electrons injected through a single quantum point contact. They observed double peaks in the distribution with the point contact quantized in two modes. The authors calculation of the distribution using a Fraunhofer diffraction approximation through a quantized single slit agreed well with results. In this calculation they use a Greens function in weak magnetic fields and constructed mirror images there. They also investigated the possibility of observing interference in the angular distribution between the first and second modes, and found that the interference terms of the angular distribution were cancelled due to system symmetry. Another possible way to observe interference is due to electron waves through double point contacts. To measure this interference, the authors developed submicron air bridges to make double point contacts with independently controlled widths. The authors measured the controlled additivity of the conductance for four point contacts.

A new symbol timing synchronization for OFDM based WLANs

A new symbol timing synchronization method for OFDM based WLANs is proposed. The proposed method, which is based on the preamble structure of the IEEE 802.11a combines auto-correlation and cross-correlation algorithms where the thresholds are adaptively adjusted according to the received signal power. The proposed method with low implementation complexity enables a rapid and accurate synchronization even under very low SNR, large carrier frequency offset and multipath fading channels. The simulation results based on the IEEE 802.11a standard are presented to show the effectiveness of the proposed method.

Angular distribution of electrons injected through a quantum point contact

Abstract This paper reports on the measurement of the angular distribution of electrons injected through a quantum point contact. We observed double peaks in the distribution with the point contact quantized in two modes. Our calculation of the distribution using an approximation of Fraunhofer diffraction through a quantized single slit agreed well with results. This paper also discusses the interference between the first and second modes, and shows how the terms of interference in the angular distribution are canceled.

Flexible Signal Processing Platform Chip for Software Defined Radio with 103 GOPS Dynamic Reconf1gurable Logic Cores

Software defined radio (SDR) is expected to be a progressive technology for wireless communications under multi-communication systems. SDR requires high performance, low power consumption, and short latency hardware. We have developed a single-chip baseband processing LSI for SDR based on a hybrid architecture of coarse-grain reconfigurable logic cores and flexible accelerator modules to achieve the required features. The maximum performance is 103 GOPS. Moreover, we implemented IEEE 802.11a and IEEE 802.11b, and show the effectiveness in latency.

10-ns row cycle DRAM using temporal data storage buffer architecture

We propose a fast row-cycle DRAM-core architecture, which employs temporal data storage buffers in the sense amplifier and pipelined row-address decoding. The temporal data storage buffers eliminated the restoring time and reduced the bit-line precharge time. The pipelined row-address decoding reduced the skew in its decoding operation. We confirmed a 10 ns row-access cycle time by SPICE simulations based on a 0.24 /spl mu/m DRAM technology.

A 0.9 V sense-amplifier driver for high-speed Gb-scale DRAMs

We proposed a new sense-amplifier driver for low power, high-speed Gb-scale DRAMs. Our sense amplifier is temporally isolated from the bit line and we use overdriving with boost capacitors, to operate at a Vcc of down to 0.8 V. A charge recycle technique using a new charge-transfer transistor driver is employed to reduce power consumption in the additional controlling circuits. SPICE simulation showed that the access time was 2.7 ns faster than the conventional method, and the power consumption to isolate the bit lines and overdrive the sense amplifier was reduced by 28% using the charge recycle technique.

Arsenic precipitation from thin surface layers of low‐temperature grown GaAs

Arsenic precipitation from a thin, 100‐nm surface layer of GaAs grown at low temperature (LT) by molecular beam epitaxy is investigated. The precipitate depth distribution is examined for different rapid thermal annealing cycles. It is found that the precipitate distribution can tail a long distance into the underlying stoichiometric GaAs layer, depending on the peak annealing temperature. The distribution for an 800 °C anneal is virtually unaffected by a prior low temperature ‘‘soak’’ at 600 °C, thus showing that the precipitation is insensitive to the initial point defect concentrations in this temperature range. The relevance of these results to the precipitation process and to the use of thin LT layers in device applications is discussed.

Cyclic reconfiguration for pipelined applications on coarse-grain reconfigurable circuits

A new reconfiguration technique for pipelined applications on coarse-grain reconfigurable circuits, the cyclic reconfiguration method, is proposed. In this method, the configurations that have interleaved pipeline stages are switched once per clock. This method improves the ratio of effective processing elements in one configuration plane, and the number of switching configuration planes is reduced. As a result, throughput is improved. In comparison with a FIR filter, throughput by the cyclic reconfiguration method is two times the throughput of the previously introduced incremental reconfiguration method.