Hisashi Iwamoto

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7- mu m CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm/sup 2/ is only a 7% increase over the conventional 4-Mb DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity. >