Yasuhiro Konishi

Analysis of coupling noise between adjacent bit lines in megabit DRAMs

Different bit-line structures, bit-line materials, widths, spacings, and passivation materials were fabricated to analyze the effect of the coupling noise between adjacent bit lines in megabit DRAMs. Each component of total bit-line capacitance was measured to obtain the bit-line-to-bit-line capacitance and the other contributions to the total bit-line capacitance. Accelerated soft error tests were performed on each sample. The results suggest the existence of two types of noise effects. One is the READ-signal degradation just after the work-line rises. The other is the disturbance in sensing operation. The larger the ratio of the bit-line coupling capacitance to the other bit-line capacitance contributions the more serious both the noise effects are. These noise mechanisms can be explained by the charge conservation model and the simulation of sensing operation. A polycide bit-line structure is less susceptible to these noises than an Al bit line because its thickness and layer position. >

A 34-ns 16-Mb DRAM with controllable voltage down-converter

A high-speed 16-Mb DRAM with high reliability is reported. A multidivided column address decoding scheme and a fully embedded sense-amplifier driving scheme were used to meet the requirements for high speed. A low-power hybrid internal power supply voltage converter with an accelerated life-test function is also proposed and was demonstrated. A novel substrate engineering technology, a retrograded well structure formed by a megaelectronvolt ion-implantation process, provides a simple process sequence and high reliability in terms of soft error and latch-up immunity. >

A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

A 4-Mb DRAM that has 38-ns RAS (row-address-strobe) access time and a battery-backup (BBU) mode, and retains data with a 44- mu A current requirement is described. The BBU mode is a self-refresh mode. Its power dissipation, however, is reduced in comparison with that of a normal refresh operation. The memory can operate as a standard 4-Mb DRAM, without any timing constraint on CAS (column-address-strobe) and RAS, if the operating cycle does not exceed 16 ms. This approach promises more stable supply at lower cost than specially provided counterparts such as pseudo-SRAMs.<<ETX>>

Highly reliable testing of ULSI memories with on-chip voltage-down converters

Two testing techniques for ultra-large-scale integrated (ULSI) memories containing on-chip voltage downconverters (VDCs) are described. The first in an on-chip VDC tuning technique that adjusts internal V/sub CC/ to compensate for the monitored characteristics of the process parameters during repair analysis testing. The second is an operating-voltage margin test, performed at various internal V/sub CC/ levels during the water sort test (WT) and the final shipping test (FT).<<ETX>>

A 180 MHz multiple-registered DRAM for low-cost 2 MB/chip secondary cache

A Multiple-registered DRAM is described for 2 MB/chip secondary cache. 64 registers per bank of the RAM enable the data transfer from 64 dynamic memory cells to the registers simultaneously, realizing 180 MHz cache fill operation. The area increase with the architecture is only 5.4% over the conventional DRAM, which contributes to realize low-cost high-performance cache systems.<<ETX>>

400-MHz random column operating SDRAM techniques with self-skew compensation

High-speed data transfer is a key factor in future main memory systems. DDR SDRAM (double-data-rate synchronous-DRAM) is one of the candidates for high-speed memory. In this paper we present three techniques to achieve a short access time and high data transfer rate for DDR-SDRAMs. First, a self-skew compensating technique enables 400-Mbit/s address and data detection. Second, a novel trihierarchical WL scheme realizes multibank operation without access or area penalties. Third, an interleaved array access path doubles the array operating frequency and it enables 400-MHz random column operation. A 16-bank 256-Mbit DDR SDRAM circuit has been designed, and the possibility of the realization of random column 200 MHz/spl times/32 DDR operation, namely, 1.6-Gbyte/s data rate operation, has been confirmed.