Hisashi Kino

New heterogeneous multi-chip module integration technology using self-assembly method

We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mum were electrically connected by unique lateral interconnections formed crossing over chip edges with large step height. We evaluated fundamental electrical characteristics using daisy chains formed crossing over test chips which were face-up bonded onto the substrates by the self-assembly. We obtained excellent characteristics in these daisy chains. In addition, RF test chips with amplitude shift keying (ASK) demodulator and signal processing circuits were self-assembled onto the substrates and electrically connected by the lateral interconnections. We confirmed that these test chips work well.

MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and

We report high-performance MOSFET nonvolatile memory with high-density cobalt-nanodots (Co-NDs) floating gate (the density is as high as 4-5 × 1012 /cm 2 and the size is ~2 nm) and HfO2 high-k blocking dielectric. The device is fabricated using a gate-last process. A large memory window, high-speed program/erase (P/E), long retention time, and excellent endurance till 106 P/E cycles are obtained. In addition, the discrete Co-NDs make dual-bit operation successful. The high performance suggests that high work-function Co-NDs combined with high-k blocking dielectric have a potential as a next-generation nonvolatile-memory candidate.

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A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.

High-k Blocking Dielectric

A three-dimensional LSI (3D-LSI) that vertically stacks Si chips with a number of through-silicon vias (TSVs) and metal microbumps has attracted much attention recently. However, there are some issues to be resolved in the fabrication of 3D-LSI. In this study, we investigated impacts of local bending stress on the performance of a complementary metal–oxide–semiconductor (CMOS) circuit fabricated in a thinned Si chip. First, we proposed a novel method and a test structure to easily induce the local bending stress in the thinned Si chip. Then, we evaluated the distribution of the local bending stress and its effects on the electrical characteristics of metal–oxide–semiconductor field-effect transistor (MOSFETs). As a result, we observed the degradations of the MOSFET currents and CMOS inverter switching behaviors in accordance with the chip local bending. Our experimental results obviously indicate that the local bending stress caused large fluctuations in the performance of the circuit fabricated in the thinned Si chip.

Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu–SnAg Microbumps and a Nonconductive Film

Silicon-lattice distortion in the 50- μm-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45° and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ~ 1000 MPa of tensile stress and ~ -200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.

Investigation of Local Bending Stress Effect on Complementary Metal–Oxide–Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration

The self-assembly of known good dies on hosting substrates using liquid surface tension is a promising technology to create highly integrated 3-D and heterogeneous microelectronic systems. In this paper, we investigate the effects of the edge structures of self-assembled chips on alignment accuracies. Nine types of 100-μm-thick Si chips (3 mm × 3 mm) with and without step geometries on their hydrophilic or hydrophobic peripheries are self-assembled onto hydrophilic assembly sites formed on planar- and plateau-type host substrates. When hydrophobic peripheries with step geometries are applied to both the edges of chips and assembly sites formed on substrates, the resulting average alignment accuracy is 300 nm. Total accuracy variation within 2 μm is realized by using either chip or substrate having 10-μm-height step structures with hydrophobic edges. We obtain a high tolerance for initial offsets indicating positioning misalignment prior to chip release, with the plateau-type substrates and the chips having hydrophobic step structures at the edges. These chips are precisely self-assembled, even under a large initial offset of 1.5 mm in a horizontal direction to both the substrates. The extremely large offset is comparable with 50% of the side length of the 3-mm-square chip. On the other hand, the chips formed by an accurate saw dicing that gives high chip-size accuracies as designed exhibit high alignment accuracies and tolerances when compared with the chips with the hydrophobic step structures and the chips formed by plasma dicing, which offer a large pseudo step with a height of 100 μm.

Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice

We have proposed a new multichip-to-wafer 3D stacking method with high throughput and high yield based on a capillary self-assembly method using liquid droplets. In this paper, we optimized conditions in self-assembly and microbump bonding using non-conductive film (NCF)-covered known good dies (KGDs). Self-assembly of the NCF-covered KGDs provided high chip alignment accuracy within approximately 1 μm. After the self-assembly and a subsequent thermal compression, resultant microbump chains composed of over 7,000 microbump joints exhibited good electrical properties of 32 mΩ/joint without bridge short and open failures. The microbump joint resistance varied within 5% of the initial values after thermal cycle test (TCT) of 1,000 cycles. In addition, we demonstrated a multi-layer 3D stacking by the self-assembly method with the NCF-covered KGDs.

Impact of Chip-Edge Structures on Alignment Accuracies of Self-Assembled Dies for Microelectronic System Integration

Twelve-channel vertical-cavity surface-emitting laser (12-ch VCSEL) chips are heterogeneously self-assembled on Si and glass wafers using water surface tension as a driving force. The VCSEL chips have a high length-to-width aspect ratio, that is, 3 mm long and 0.35 mm wide. The VCSEL chips are precisely self-assembled with alignment accuracies within 2 ?m even when they are manually placed on liquid droplets provided on the host substrate. After the self-assembly of the VCSEL chips and the subsequent thermal compression, the chips successfully emit 850 nm light and exhibit no degradation of their current?voltage (I?V) characteristics.

Development of highly-reliable microbump bonding technology using self-assembly of NCF-covered KGDs and multi-layer 3D stacking challenges

Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration. The remnant stress existing after wafer thinning was evaluated using angle-(5°) polished silicon wafers by micro-Raman spectroscopy (μRS). The metal contamination in the thinned silicon substrates has been evaluated by a capacitance - time (C-t) measurement method using MOS capacitors in which the thinned silicon substrates were diffused with metallic impurities such as Cu and Au used for through-silicon via (TSV) and metal micro-bump in 3D LSI.

Vertical-cavity surface-emitting laser chip bonding by surface-tension-driven self-assembly for optoelectronic heterogeneous integration

A local bending stress is induced by coefficient of thermal expansion (CTE) mismatch between underfill material and metal microbumps in three-dimensional IC (3D IC). A high concentration of filler in underfill is effective to suppress the local bending stress. However, it is difficult to apply high concentration of filler due to fine pitch microbumps. On the other hand, manganese nitride-based compound has large negative CTE compared with conventional negative-CTE materials. In this study, we have investigated the effect of manganese nitride-based filler on local bending stress induced by CTE mismatch between underfill and metal microbumps in 3D IC. We observed that manganese nitride-based filler can decrease CTE of underfill compared with conventional silica-based filler. This result indicated that manganese nitride-based filler can reduce keep-out-zone (KOZ) in 3D IC by local bending stress suppression.