Seiya Tanikawa

Degradation of Memory Retention Characteristics in DRAM Chip by Si Thinning for 3-D Integration

The Youngs modulus (E) of Si substrate begin to noticeably decrease below 50-μm thickness. The Youngs modulus in 30-μm thick Si substrate decreased by 30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, the lattice structure of Si atom is highly distorted. Large distortion of the lattice structure induces the Youngs modulus reduction, consequently weakens the mechanical strength. A DRAM chip of 200-μm thickness is bonded to a Si interposer and thinned down to 50/40/30/20-μm thickness, respectively. The retention characteristics of DRAM cell are degraded depending on the decreasing of the chip thickness, especially dramatically degraded below 50-μm thickness. The retention time of DRAM cell in the 20- μm thick chip is shortened by ~ 40% compared to the 50-μm thick chip, regardless of the well structure (triple-well, twin-well). The distortion of the lattice structure in the thin chip effects carrier recombination rates, consequently a shortening retention time of DRAM cell.

Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM

The impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip were evaluated. The retention characteristics of DRAM cell in a DRAM chip which was face-down bonded to an interposer with under-fill degraded depending on the decreased chip thickness, especially dramatically degraded below 40- μm thickness. Meanwhile, the retention characteristics of DRAM cell in a DRAM chip which was bonded without under-fill relatively not so degraded until to 30- μm thickness, but suddenly degraded below 20- μm thickness. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300 °C annealing, regardless of the well structure. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip which was DP-treated not degraded even after Cu diffusion at 300 °C annealing.

Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-μm thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300°C, 30 min. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip, which was DP-treated, is not degraded even after annealing. The retention characteristics of some memory cells separated by 20-μm ~ 50-μm from arrays of 10-μm diameter Cu TSVs began to degrade after post-annealing at 300°C, 30 min owing to the in-sufficient blocking property of the sputtered-Ta barrier layers in TSV array. The CVD Mn oxide layer formed as a barrier layer in the TSVs shows better barrier property results compared with the sputtered Ta barrier layer.

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory

The Youngs modulus (E) of Si substrate begins to noticeably decrease below 50-μm thickness. The Youngs modulus in 30-μm thick Si substrate decreased by approximately 30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, the lattice structure of Si substrate is highly distorted. Large distortion of the lattice structure induces the Youngs modulus reduction, consequently weakens the mechanical strength. A DRAM chip of 200-μm thickness was bonded to a Si interposer and thinned down to 50/40/30/20-μm thickness, respectively. The retention characteristics of DRAM cell are degraded depending on the decreased chip thickness, especially dramatically degraded below 50-μm thickness. The retention time of DRAM cell in 20-μm thick chip is shortened by approximately 40% compared to the 50-μm thick chip, regardless of the well structure (triple-well, twin-well). The distortion of the lattice structure in the thin chip effects a minority carrier generation lifetime, consequently shortening the retention time of DRAM cell.

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC

Three-dimensional IC (3D IC) has attracted much attention as a promising method to enhance IC performance. Recently, great interests in mechanical reliability are increasing among 3D IC researchers for production of 3D IC. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive called underfill material. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE difference induces local bending stress in thinned IC chips. This local bending stress would affect transistor reliability in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we present design guideline of microbump layout which can suppress the local bending stress in 3D-stacked several thin IC chips.

Minimization of Keep-Out-Zone (KOZ) in 3D IC by local bending stress suppression with low temperature curing adhesive

Three dimensional IC (3D IC) has lots of through-Si vias (TSVs) and metal microbumps for electrical connection between stacked IC chips, and also has organic adhesives to enhance the mechanical strength of 3D IC. However, the coefficient of thermal expansion (CTE) mismatch between microbumps and organic adhesives generate the local bending stress in thinned IC chips. Therefore, Keep-Out-Zone (KOZ) for transistors must be considered in 3D IC design to eliminate characteristic fluctuations and degradations due to the local bending stress. In this study, for the first time, we evaluated the effects of low temperature curing adhesive on both the local bending stress and the resultant transistor characteristics for decrease in KOZ of 3D IC.

Evaluation of in-plane local stress distribution in stacked IC chip using dynamic random access memory cell array for highly reliable three-dimensional IC

As three-dimensional (3D) ICs have many advantages, IC performances can be enhanced without scaling down of transistor size. However, 3D IC has mechanical stresses inside Si substrates owing to its 3D stacking structure, which induces negative effects on transistor performances such as carrier mobility changes. One of the mechanical stresses is local bending stress due to organic adhesive shrinkage among stacked IC chips. In this paper, we have proposed an evaluation method for in-plane local stress distribution in the stacked IC chips using retention time modulation of a dynamic random access memory (DRAM) cell array. We fabricated a test structure composed of a DRAM chip bonded on a Si interposer with dummy Cu/Sn microbumps. As a result, we clarified that the DRAM cell array can precisely evaluate the in-plane local stress distribution in the stacked IC chips.

Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors

Three-dimensional integrated circuit (3D IC) is one of the promising ways to enhance IC performance. Each IC chip is mechanically connected by organic adhesive and metal microbumps. Coefficient of thermal expansion (CTE) mismatch between materials causes local bending stress in IC chips, leading to negative effects in IC performance. In this study, we have fabricated a test structure with DRAM cell array having planar MOS capacitors. Using the test structure, we measured both DRAM chip bending profiles and retention time modulations of DRAM cell array. Consequently, we have successfully demonstrated that the local bending stress in IC chips can be two-dimensionally evaluated using the DRAM cell array with planar MOS capacitances. This evaluation methods leads to realization of 3D IC with high reliability.

Minimized hysteresis and low parasitic capacitance TSV with PBO (polybenzoxazole) liner to achieve ultra-high-speed data transmission

Through-Si-via (TSV) with polymer liner formation has attracted considerable attention because a polymer liner can be formed easily by spin coating, and it has low dielectric constant and good coverage along the TSV surface. A polyimide (PI) was used as the polymer liner of TSV. However, there is a high charge-trap density in the PI layer. These charge traps leads to modulation of the parasitic capacitance present between the TSV metal and the Si substrate. Therefore, in this paper, we propose the deployment of polybenzoxazole (PBO) as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structure was fabricated with PBO and PI liners. Further, capacitance-voltage (C-V) characteristics of the fabricated MOS capacitor were evaluated. In case of the PBO liner, remarkable suppression of the C-V curve shift was observed as compared to that of the PI liner. These results indicate that the PBO is a promising TSV liner material for realizing high-performance, high-reliability, and low-cost three-dimensional stacked ICs.

Impact of local stress in 3D stacking process on memory retention characteristics in thinned DRAM chip

The effect of local stresses on memory retention characteristics has been characterized in detail. A retention time of memory cells in a DRAM chip with 200-μm thick was largely changed after under-fill shrinkage with Cu/Sn bumps. Meanwhile, after thinned down to 40-μm thick, the retention time of memory cell was not significantly changed in the whole area even with Cu/Sn bumps due to decreased stress. We showed that the local stress generated by under-fill shrinkage with the dummy Cu/Sn bumps gave larger effects on the memory retention characteristics than the stress generated by the Si thinning until 40-μm thick.