Takeo Ushiki

Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing

A reliable tantalum (Ta)-gate device technology, which can drastically reduce the number of process steps, has been developed. Ta-gate fully-depleted-silicon-on-insulator (FDSOI) MOSFETs with 0.15-/spl mu/m gate length by low-temperature processing below 500/spl deg/C after the gate oxide formation have good on/off characteristics. Comprehensive design guidelines for Ta-gate MOSFETs in the deep-submicrometer regime is provided by investigating a wide range of performance and reliability constraints on the process temperature and the SOI thickness. In the guideline, the recrystallization of the source/drain region gives inferior limits of the SOI thickness and the process temperature. Thermal reaction between Ta and SiO/sub 2/ films sets a superior limit of the process temperature, and a short-channel effect sets a superior limit of the SOI thickness.

Chemical reaction concerns of gate metal with gate dielectric in Ta gate MOS devices: an effect of self-sealing barrier configuration interposed between Ta and SiO/sub 2/

Chemical reaction of gate metal with gate dielectric for Ta gate MOS devices has been experimentally investigated both by electrical and physical measurements: capacitance-voltage (C-V), current-voltage (I-V), transmission electron microscopy (TEM), energy dispersive X-ray (EDX), electron diffraction measurements. In spite of the chemical reaction of Ta with SiO/sub 2/ consuming /spl sim/1-nm-thick in gate oxide, the interface trap densities of /spl sim/2/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/ at midgap and ideal channel mobility characteristics have been observed in the Ta gate MOS devices with 5.5-nm-thick thermal oxide gate dielectric. Considering the experimental data with theoretical calculation based on thermodynamics together, a barrier layer model has been developed for the Ta gate MOS systems. The physical mechanism involved is probably self-sealing barrier layer formation resulting from the chemical reaction kinetics in the free-energy change of Ta-Si-O system.

Threshold voltage adjustment in SOI MOSFETs by employing tantalum for gate material

The threshold voltages of n-channel and p-channel thin-film Si-on-Insulator (SOI) MOSFETs have been controlled by employing Tantalum (Ta) for gate materials in 1 V applications. The threshold voltage control in SOI MOSFETs by the work function of gate material, that is, work function engineering is needed. In order to suppress the reaction between Ta and gate oxide, low-temperature processing after the gate oxide step was successfully established.

Gate oxide reliability concerns in gate-metal sputtering deposition process: an effect of low-energy large-mass ion bombardment

Abstract The effects of ion species/ion bombardment energy in sputtering deposition process on gate oxide reliability have been experimentally investigated. The use of xenon (Xe) plasma instead of argon (Ar) plasma in tantalum (Ta) film sputtering deposition for gate electrode formation makes it possible to minimize the plasma-induced gate oxide damage. The Xe plasma process exhibits 1.5 times higher breakdown field and five times higher 50%-charge-to-breakdown ( Q BD ). In the gate-metal sputtering deposition process, the physical bombardment of energetic ion causes to generate hole traps in gate oxide, resulting in the lower gate oxide reliability. The simplified model providing a better understanding of the empirical relation between the gate oxide damage and the ion-bombardment energy to gate oxide in gate-metal sputtering deposition process is also presented.

New aspects and mechanism of kink effect in static back-gate transconductance characteristics in fully-depleted SOI MOSFETs on high-dose SIMOX wafers

An extraordinary kink phenomenon in static back-gate transconductance characteristics of fully-depleted SOI MOSFETs has been experimentally investigated and characterized for the first time. This kink phenomenon has been observed in both NMOS and PMOS on high-dose SIMOX wafers under steady-state conditions at room temperature. It was also found that the back-gate characteristics for both NMOS and PMOS show anomalous shift phenomenon in drain current-back gate voltage (I/sub D/-V/sub G2/) curve at the back-gate voltage corresponding to the kink phenomenon. This kink phenomenon has been attributed to the presence of energetically-localized trap states at SOI/BOX interface. In order to clarify the energy level of the trap states at SOI/BOX interface corresponding to the kink, we have developed a new formula of surface potential in thin-film SOI MOS devices, in which the potential drop across semiconductor-substrate is taken into account. By using this new formula, me have demonstrated that high-dose SIMOX wafers have donor-like electron trap states at /spl sim/0.33 eV above the Si midgap with the density of /spl sim/N6.0/spl sim/10/sup 12/ cm/sup -2/ eV/sup -1/ and donor-like hole trap states at /spl sim/0.35 eV below the Si midgap with density of /spl sim/1.5/spl times/10/sup 12/ cm/sup -2/ eV/sup -1/ at SOI/BOX interface.

Improvement of gate oxide reliability for tantalum-gate MOS devices using xenon plasma sputtering technology

The effects of ion species in the sputtering deposition process on gate oxide reliability have been experimentally investigated. The use of xenon (Xe) plasma instead of argon (Ar) plasma in tantalum (Ta) film sputtering deposition for gate electrode formation makes it possible to improve the gate oxide reliability. The Xe plasma process exhibits 1.5 times higher breakdown field and five times higher 50%-charge-to-breakdown (Q/sub BD/). In the Ta sputtering deposition process on gate oxide, the physical bombardment of energetic inert-gas ion causes the generation of hole trap sites in gate oxide, resulting in the lower gate oxide reliability. A simplified model providing a better understanding of the empirical relation between the gate oxide damage and the inert-gas ion bombardment energy in the gate-Ta sputtering deposition process is also presented.

Tantalum-gate SOI MOSFET's featuring excellent threshold voltage control in low-power applications

In this paper it is successfully demonstrated that Ta-gate SOI MOSFETs have excellent threshold voltage control in 1V applications.

Reduction of plasma-induced gate oxide damage using low-energy large-mass ion bombardment in gate-metal sputtering deposition

The effects of ion species in the sputter deposition process on gate oxide reliability have been experimentally investigated. The use of xenon (Xe) plasma instead of argon (Ar) plasma in tantalum (Ta) film sputter deposition for gate electrode formation makes it possible to improve the gate oxide reliability. The Xe plasma process exhibits 1.5 times higher breakdown field and 5 times higher 50%-charge-to-breakdown (Q/sub BD/). In the gate-metal sputter deposition process, the physical bombardment of energetic ions causes generation of hole traps in the gate oxide, resulting in lower gate oxide reliability. A simplified model providing a better understanding of the empirical relationship between the gate oxide damage and the ion bombardment energy in the gate-metal sputter deposition process is also presented.

High-performance metal-gate SOI CMOS fabricated by ultraclean low-temperature process technologies

The threshold voltages of thin-film fully-depleted Si-on- insulator (FDSOI) nMOS and pMOS have been controlled by employing tantalum (Ta), one of the high-refractory metals, for the gate material. For the low-power application in deep quarter-micron regime, when the supply voltage becomes around 1.0 V, it is necessary that the threshold voltages of SOI MOSFETs, are controlled by the work function of the gate material: Work Function Engineering. It is clear that the mid-gap material instead of the poly-crystalline silicon (poly-Si) for the gate material is effective to control the threshold voltage. The use of the mid-gap material leads to the simplicity for CMOS processes because the same gate material is available for both nMOS and pMOS. Ta, one of the mid-gap material, has low resistivity and excellent durability to wet chemical cleaning. The ultraclean, low- temperature process makes it possible to suppress the reaction between Ta and the gate oxide. The results have shown that Ta-gate FDSOI MOSFET exhibits excellent threshold voltage adjustment in 1.0 V application, even if the gate length is reduced to 0.15 micrometers .