Hitesh Shrimali

Distortion Analysis of a Three-Terminal MOS-Based Discrete-Time Parametric Amplifier

Distortion associated with a three-terminal MOS parametric amplifier has been analyzed using Volterra series. A prototype design of an nMOS-based parametric amplifier with supporting circuits was integrated on a standard 0.13-μm CMOS technology. The measurement results and the theoretical characterization show a mean percentage error of 16% and 1.25% for second harmonic (A2) and third harmonic (A3), respectively.

CMOS IC RADIATION HARDENING BY DESIGN

Design techniques for radiation hardening of integrated circuits in commercial CMOS technologies are presented. Circuits designed with the proposed approaches are more tolerant to both total dose and to single event effects. The main drawback of the techniques for radiation hardening by design is the increase of silicon area, compared with a conventional design.

11 GHz UGBW Op-amp with feed-forward compensation technique

A high speed pseudo differential three stage operational amplifier has been implemented using a feed-forward compensation technique in a standard 0.13 µm CMOS technology. The three stage inverter based op-amp with feed-forward compensation achieves 11 GHz of unity gain bandwidth for a nominal power consumption 18 mW, and exhibits 39 dB of DC gain with phase margin of 62° when driving a differential load of (2×300 fF) at a 1.2 V power supply voltage. At a power supply voltage as low as 0.4 V, the same circuit consumes 0.1 mW and achieves 79 MHz of unity gain bandwidth. The proposed op-amp achieves a figure of merit (FOM) [1] of 440 at 1.2 V, and 190 at 0.4 V.

The start-up circuit for a low voltage bandgap reference

This paper proposes the startup circuit for a low voltage CMOS bandgap reference circuit. The all MOS scalable voltage bandgap reference (BGR) circuit has been designed and simulated using a standard 65 nm CMOS technology. The proposed startup circuit is simple, smaller in size and uses the feedback mechanism. The BGR circuit provides 661.54 mV of the voltage reference and 9 μA of the current reference with the temperature sensitivity of 4.23 ppm/°C. The total power consumption of the BGR and the startup circuitries are 243 μW and 148 nW respectively.

The pole-zero doublet: A cascode operational amplifier with cross coupled capacitor

A symbolic analysis is presented to investigate the effect of cross coupled capacitor on a cascode operational amplifier. A complete transfer function of the amplifier with cross coupled capacitor is derived and verified through circuit simulations. The modeled transfer function shows presence of a pole-zero doublet in the amplifiers frequency response when the cross-coupled capacitor is connected across it. The analysis further results in a closed form equations to optimize the amplifier based on user defined specifications such as, an open loop dc gain, a unity gain bandwidth and a phase margin. To check the validity of the model, a 50 dB open loop dc gain and 255 MHz unity gain bandwidth cascode amplifier is designed in a standard 90 nm CMOS technology with the supply voltage of 1.5 V. The results obtained from simulation and modeled transfer function show good agreement with each other and have an acceptable average relative error of 3 %.

Third order harmonic cancellation technique for a parametric amplifier

This work presents a feed-forward technique to reduce the third order harmonic distortion of a parametric amplifier. A prototype design of an nMOS based differential parametric amplifier with supporting circuits were integrated on a standard 0.13 µm CMOS technology. A comparison between a regular parametric amplifier, and a parametric amplifier with feed-forward distortion cancellation, demonstrates a mean reduction of third order harmonic distortion of −13 dB. This comes at a cost of a maximum gain reduction of 0.9 dB.

Characterization of HV-CMOS detectors in BCD8 technology and of a controlled hybridization technique

Radiation detectors built in high-voltage and high-resistivity CMOS technology are an interesting option for the large area pixel-trackers sought for the upgrade of the Large Hadron Collider experiments. A characterisation of the BCD8 technology by STMicroelectronics process has been performed to evaluate its suitability for the realisation of CMOS sensors with a depleted region of several tens of micrometer. Sensors featuring

Systematic design approach for a gain boosted telescopic OTA with cross-coupled capacitor

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HV-CMOS detectors in BCD8 technology

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