Valentino Liberali

TOSCA: a simulator for switched-capacitor noise-shaping A/D converters

A software tool named TOSCA (Tool for Oversampled Switched-Capacitor A/D Converter Analysis) is described. The simulator is behavioral, general purpose and fully user-friendly. Because a set of basic building blocks is available, generic switched-capacitor noise-shaping A/D converters can be analyzed simply by building netlist file. Two hierarchical levels have been considered for circuit description: block level for subcircuits like quantizers and digital filters, and component level for subcircuits like the integrators where switches, capacitors and operational amplifiers are used as building elements. The developed models allow the most relevant nonideal parameters of the components to be taken into account, and a set of postprocessing facilities allows extensive analysis of the circuits. The program is written in C language, uses dynamic memory allocation, and is very fast. >

Evolution in the criteria that underlie the design of a monolithic preamplifier system for microstrip detectors

Abstract Several steps through which the design of a monolithic preamplifier system for microstrip detectors has passed, are critically analyzed. From the very initial MOSFET version, several measures were gradually taken with the purpose of reducing noise. The latest design criteria aim at realizing a preamplifier system which, besides outstanding noise performances, features also a suitable degree of radiation tolerance.

A Smart Sensor System for Carbon Monoxide Detection

This paper illustrates a smart sensor system for carbonmonoxide detection. An innovative technological approach hasbeen pursued to fabricate gas sensors on silicon substrate, compatiblewith IC fabrication. A mixed analog-digital electronic interfaceprocesses the outputs of three sensors to compensate relativehumidity and interfering gases. Sigma-delta signal processingand low-frequency noise reduction techniques are used to minimizesilicon area and to meet the required performance in a standardCMOS technology.

Model and verification of triple-well shielding on substrate noise in mixed-signal CMOS ICs

In this work, the effect of triple-well shielding in mixed signal CMOS integrated circuits is studied. A test chip is presented that contains structures intended for investigation on substrate noise coupling. This paper shows experimental results, giving a rationale for them and providing design guidelines.

Full stacked layout of analogue cells

A program for the automatic layout of analogue CMOS cells using the full stacked approach is described. The stacked approach consists of the division of large transistors into several parallel elementary transistors, and of their accommodation in one or more parallel stacks made of the same number of transistors. The general rules for the design of stacked structures are discussed, and topological solutions of some popular schemes of operational amplifiers are presented. The stacked architecture is generated in a symbolic way, and it is automatically translated into the physical layout on the basis of the geometrical parameters and the technological design rules.<<ETX>>

An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters

An evolutionary algorithm is used to design a finite impulse response digital filter with reduced power consumption. The proposed design approach combines genetic optimization and simulation methodology, to evaluate a multi-objective fitness function which includes both the suitability of the filter transfer function and the transition activity of digital blocks. The proper choice of fitness function and selection criteria allows the genetic algorithm to perform a better search within the design space, thus exploring possible solutions which are not considered in the conventional structured design methodology. Although the evolutionary process is not guaranteed to generate a filter fully compliant to specifications in every run, experimental evidence shows that, when specifications are met, evolved filters are much better than classical designs both in terms of power consumption and in terms of area, while maintaining the same performance.

Design of a rad-hard library of digital cells for space applications

This paper proposes a design methodology for a digital library of cells resistant to cosmic radiation. Most important effects due to radiation are avoided or mitigated using ad hoc design techniques. Fault injection techniques are used to validate the design. Simulations results demonstrate that the cells designed in a 180 nm CMOS technology are tolerant to 1.5 mA current peak due to interaction with a single high-energy particle.

TOSCA: a user-friendly behavioural simulator for oversampling A/D converters

The potential and flexibility of use of the software tool TOSCA is presented. The tool proved to be fully user-friendly for the design of Sigma Delta A/D converters. Modulator and decimator structures can easily be designed simply by using a set of basic building blocks and applying adequate analysis commands. Simulation results were presented for the example of a two-stage MASH Sigma Delta A/D converter.<<ETX>>

Associative memory design for the fast track processor (FTK) at ATLAS

We propose a new generation of VLSI processors for pattern recognition, based on associative memory architecture, optimized for online track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new associative memory project: it maximizes the pattern density on the ASIC, minimizes the power consumption and improves the functionality for the fast tracker processor proposed to upgrade the ATLAS trigger at LHC.

On-line evolution of FPGA-based circuits: a case study on hash functions

An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. An experimental study is carried out to determine the best set of parameters for on-line execution. It is observed that small population size leads to more effective results when short execution time is required. An application of the evolutionary approach presented in the paper for on-line tuning of the function during cache memory operation is also discussed.