Shouri Chatterjee

A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC

A 0.5-V third-order one-bit fully-differential continuous-time DeltaSigma modulator is presented. The presented modulator architecture uses true low-voltage design techniques, and does not require internal voltage boosting or low-threshold devices. A return-to-open architecture that enables the ultra-low-voltage realization of return-to-zero signaling for the feedback DAC is proposed. The ultra-low-voltage operation is further enabled by a body-input gate-clocked comparator, and body-input operational transconductance amplifiers for the active-RC loop filter. Fabricated on a 0.18-mum CMOS process, the modulator achieves a peak SNDR of 74 dB in a 25 kHz bandwidth, and occupies an area of 0.6 mm2; the modulator core consumes 300 muW.

A 0.5-V bulk-input fully differential operational transconductance amplifier

We present a fully differential two-stage Miller op-amp operating from a 0.5 V power supply. The input signal is applied to the bulk nodes of the input devices. A prototype was designed in a standard 0.18 /spl mu/m CMOS process using standard 0.5 V V/sub T/ devices. It has a measured 52 dB DC gain, a 2.5 MHz gain-bandwidth and consumes 110 /spl mu/W.

Multi-Band Frequency Transformations, Matching Networks and Amplifiers

In this paper, a technique for the synthesis of lumped element multi-band matching networks is proposed using frequency transformations. The proposed technique has been generalized for n -bands using 1→ n frequency transformations. The effect of the transformations on the bandwidth of the matching network and the effect of inductor losses on the transducer loss of the matching network are analyzed. A strategy to improve the efficiency of the matching networks in the presence of lossy components has been proposed. Applications of the proposed synthesis technique in the development and design of new multi-band LNA/PA architectures are discussed in detail with the help of design examples. In one of the design examples, the circuit has been prototyped and measured results are presented.

Ultra-Low Voltage Analog Integrated Circuits

The operation of analog circuits from ultra low supply voltages becomes necessary due to semiconductor technology scaling. Yet traditional design techniques cannot be used. In this paper, we review techniques that allow analog circuits to operate with supply voltages as low as 0.5 V. Biasing considerations are given, and robust bias circuits are discussed. For frequency-tunable circuits, a low-voltage MOS varactor tuning technique is presented. The techniques discussed are applied to two different OTA topologies, as well as to an automatically tuned, fifth-order active RC filter. This material is largely based on the work of the authors as described in [1]-[5].

A 0.5-V 1-Msps Track-and-Hold Circuit With 60-dB SNDR

We discuss a design technique that makes possible the operation of track-and-hold (T/H) circuits with very low supply voltages, down to 0.5 V. A 0.5-V 1-Msps T/H circuit with a 60-dB SNDR is presented. The fully differential circuit is fabricated in the CMOS part of a 0.25-mum BiCMOS process, with standard 0.6-V VT devices, and uses true low-voltage design techniques with no clock boosting and no voltage boosting. The T/H circuit has a measured current consumption of 600 muA

Ultra-Low Voltage Analog Design Techniques for Nanoscale CMOS Technologies

This paper reviews the challenges and opportunities for ultra-low voltage analog integrated circuit design. The continuing scaling of CMOS technology feature sizes forces a proportional reduction of the supply voltage. The ultra-low supply voltages, down to 0.5 V, projected for the nanoscale CMOS technologies requires drastic changes in the basic circuit topologies used in analog integrated circuits. We explore the combined use of the gate and body terminal of the MOS transistor for signal input or bias control. We illustrate several true-low voltage OTA design and biasing techniques in a fully integrated 0.5 V varactor-C active filter implemented in a standard 0.18 μm CMOS technology.

A 0.5V filter with PLL-based tuning in 0.18 /spl mu/m CMOS

Design techniques that allow analog circuit operation with supply voltages as low as 0.5V are presented. A fully integrated 135kHz fifth-order elliptic LPF, including automatic bias circuits and an on-chip PLL for tuning, is implemented with standard devices in a 0.18 /spl mu/m CMOS process. The 1mm/sup 2/ chip has a measured DR of 57dB and draws 2.2mA from the 0.5V supply.

Design of concurrent multi-band matching networks

A general technique for synthesis of concurrent multi-band matching networks is proposed. The proposed design technique can be adapted to any matching strategy (noise match or conjugate match using L-match, П-match or any other topology), for multiple frequencies. Detailed design procedures are outlined for dual-band and quad-band matching networks with the help of design examples. A prototype circuit board for a quad-band matching network has been realized with discrete components and laboratory measurement results are presented.

An 18 nA, 87% Efficient Solar, Vibration and RF Energy-Harvesting Power Management System With a Single Shared Inductor

We present a modular power management system that can harvest energy from three sources simultaneously, with available power levels of 25 nW to 100 μW, with one inductor. The DC-DC converter is clocked with energize and dump pulses, and the pulse-widths are generated for constant peak inductor current and for no reversal, without current sensing. We use a comparator to reach the open-circuit-voltage (OCV)-based maximum power point (MPP), and train an oscillator to mimic the comparator output. The oscillator frequency is tuned through a successive-approximation algorithm within 11 comparator cycles. The 180 nm chip has a maximum efficiency of 87% at an input available power of 20 μW (input voltage of 0.6 V), and has an output voltage of 1.5 V.

A 300-nW Sensitive, 50-nA DC-DC Converter for Energy Harvesting Applications

A maximum-power-point-tracking DC-DC boost converter to harvest energy from sub- μW power sources is presented. For available input-power levels below 1 μW, voltage boosting is achieved by operating all circuits in the sub-threshold region, and by switching the DC-DC converter at tens of Hz, thereby reducing switching losses. The paper further explores the possibility of energizing the DC-DC inductor for an optimum duration, such that switching and resistive losses are minimized. The sub- μW energy harvesting circuit uses an area of 0.2 mm2 on a standard 180 nm CMOS process, and utilizes an auxiliary voltage source for start-up. The designed and fabricated system is more than 50% efficient when the available power is greater than 2 μW. The circuit can harvest energy whenever the available power is more than 0.3 μW. Efficiency at 0.3 μW is 25%, at 0.5 μW is 37% and at 1 μW is 48%. The complete IC consumes 50 nA for internal operations and the input voltage can be as low as 70 mV.