Hitoshi Abiko

A GHz MOS adaptive pipeline technique using MOS current-mode logic

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-/spl mu/m MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits.

Elastic-Vt CMOS circuits for multiple on-chip power control

The elastic-Vt CMOS (EVTCMOS) circuit design controls MOS transistor source (not substrate) voltages, so fabrication requires no special steps. The post-fabrication threshold voltages can be switched back and forth between high Vt (sleep mode) and low Vt (active mode), and can be also controlled as a means of reducing the sensitivity to device-parameter deviations and operating-environment variations. This results in reduction of switching time between sleep and active modes, and in reduced static power consumption in sleep mode.

A new cobalt salicide technology for 0.15-/spl mu/m CMOS devices

A new cobalt (Co) salicide technology for sub-quarter micron CMOS transistors has been developed using high-temperature sputtering and in situ vacuum annealing. Sheet resistance of 11 /spl Omega///spl square/ for both gate electrode and diffusion layer was obtained with 5-nm-thick Co film. No line width dependence of sheet resistance was observed down to 0.15-/spl mu/m-wide gate electrode and 0.33-/spl mu/m-wide diffusion layer. The high temperature sputtering process led to the growth of epitaxial CoSi/sub 2/ layers with high thermal stability. By using this technology 0.15 /spl mu/m CMOS devices which have shallow junctions were successfully fabricated.

A 500 MHz, 32 bit, 0.4 /spl mu/m CMOS RISC processor

A 500 MHz, 32 bit RISC microprocessor has been experimentally developed using an 8-stage pipelined architecture and high-speed circuits, including a 500 MHz 1 kilobyte double-stage pipelined cache, a 1.8 ns register file, a double-stage binary look-ahead carry (BLC) adder circuit, and a 500 MHz phase locked loop (PLL) frequency multiplier. Newly developed circuit-integrating techniques include a stacked power-line structure, which serves as a noise shield and also provides low bounce, a low voltage-swing interface circuit with on-chip adjustable termination resistors, a small-skew clock distribution method, and a clock synchronization circuit which provides small-skew clock among LSI chips. About 200000 transistors are integrated into a 7.90 mm/spl times/8.84 mm die area with 0.4 /spl mu/m CMOS fabrication technology. Power dissipation is 6 W at a 500 MHz operation and 3.3 V supply voltage. >

A new cobalt salicide technology for 0.15 /spl mu/m CMOS using high-temperature sputtering and in-situ vacuum annealing

A new cobalt (Co) salicide technology using high-temperature sputtering and in-situ vacuum annealing process has been developed. This technology is a simple process without additional ion implantation and metal deposition to promote silicidation and to suppress oxidation of Co film. No line width dependence of sheet resistances was achieved down to for 0.15 /spl mu/m gate electrode and 0.33 /spl mu/m for diffusion layer. Sheet resistance of 11 /spl Omega//sq. for both gate electrode and diffusion layer was obtained with 5 nm thick Co film (CoSi/sub 2/ 17.5 nm). By using this technology, 0.15 /spl mu/m CMOS devices which have shallow junctions were successfully fabricated.

A high-performance 0.18-/spl mu/m merged DRAM/Logic technology featuring 0.45-/spl mu/m/sup 2/ stacked capacitor cell

This paper presents a 0.18-/spl mu/m merged DRAM/Logic technology having a 0.45-/spl mu/m/sup 2/ stacked capacitor cell. A low-temperature Metal/Insulator/Silicon (MIS) capacitor process provides high storage capacitance in the small cell, as well as a fully compatible process with high-performance CMOS logic technologies. A robust Co-salicide technology eliminates additional process steps for a silicide block. A developed 4 Mbit test vehicle achieves a retention time of 16 ms at 110/spl deg/C even with a CoSi/sub 2/ layer remaining on all diffusion regions in the memory cells.

Device-deviation tolerant over-1 GHz clock distribution scheme with skew-immune race-free impulse latch circuits

Clock skew (and jitter) is becoming the major obstacle to high-frequency clock distribution in sub-quarter micron CMOS LSIs, because skew cannot be scaled down even by use of scaled devices and may significantly increase as a result of device and operating environment deviations. To overcome this obstacle, the authors present skew-immune race-free impulse latch circuits and a reduced-skew ring-type clocking scheme. The 1 GHz clock test chip is integrated into a 6/spl times/6 mm/sup 2/ die with 0.18 /spl mu/m CMOS and double-layer-metal technology. The supply voltage is 1.8 V. The threshold voltage of the nMOS transistors is about 0.3 V and that of the pMOS transistors is about -0.3 V. 1 GHz global clock distribution shows less than 50 ps clock skew for those points on the chip.

A 500-MHz, 0.4-/spl mu/m CMOS, 32-word by 32-bit 3-port register file

A 0.4-/spl mu/m CMOS, 32-word by 32-bit 3-port register file has been developed for use in high speed microprocessors. It features a high-speed-oriented memory structure, low threshold voltage nMOS FETs, and a short read-precharge design. This register file has been designed for use within a small-skew clock-distribution processor datapath, and experimental results show it to be capable of 500-MHz register file operations.

A 1.5% jitter PLL clock generation system for a 500-MHz RISC processor

We have developed a clock generation system for RISC processors. The system consists of two parts of a PLL, a frequency multiplier, and a phase aligner. The multiplier can multiply the input clock frequency by 2, 4, and 8, and can accomplish a wide frequency range of output clocks, from 60 MHz to 660 MHz. Jitter is reduced to 1.5% of the output clock period by separating the clock generation system into a frequency multiplier and a phase aligner, and by developing a new differential loop filter with high sensitivity phase detection. The phase aligner reduces clock skew between the processor and peripheral LSIs. The system is fabricated with 0.4-/spl mu/m CMOS triple-layer Al process technology and operated at 3.3 V.<<ETX>>

A 400 MHz, 300 mW, 8 kb, CMOS SRAM macro with a current sensing scheme

This paper describes the development of a 400 MHz, 8 kb, 0.4 /spl mu/m CMOS SRAM macro targeted for use in on-chip cache memories. A newly developed pipeline scheme uses a dynamic decoder and half-latches to increase speed by 10% over that of conventional synchronous pipeline SRAMs. Further, a newly developed current sensing scheme, resistant both to noise and to process deviations, contributes to a job reduction in power dissipation.<<ETX>>