Atsuki Ono

A GHz MOS adaptive pipeline technique using MOS current-mode logic

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-/spl mu/m MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits.

TED control technology for suppression of reverse narrow channel effect in 0.1 /spl mu/m MOS devices

In this paper, it is revealed, for the first-time, that transient enhanced diffusion (TED) causes the reverse narrow channel effect (RNCE), which has been considered as a geometrical effect in the case of shallow trench isolation (STI). We will demonstrate that the RNCE can be suppressed by TED control techniques, including (1) high ramping rate (/spl sim/300/spl deg/C/sec) RTA, (2) a defect-blocking layer containing nitrogen, and (3) post V/sub th/ adjustment I/I.

A 100 nm node CMOS technology for practical SOC application requirement

Reports a 1.0 V operation 100 nm technology node CMOS technology for generic SOC application. We have estimated that for practical SOC chip/package design, target spec of both I/sub OFF/ and I/sub G/ must be below 5 nA//spl mu/m in view of heat generation issue. The key point is how to obtain higher drive current under this I/sub OFF//I/sub G/ restriction. Taking this criteria into account, we optimized 1) the gate dielectric formation sequence consisting of RTH treatment and radical nitridation; 2) gate off-set spacer optimization for practical and robust 100 nm-node CMOS technology. Fabricated transistor, featuring 65 nm gate length and 1.6nm-EOT gate dielectric, show 640/260 /spl mu/A//spl mu/m of I/sub ON/ and 5n/5n A//spl mu/m of I/sub OFF/ with 1.0V operation.

A 70 nm gate length CMOS technology with 1.0 V operation

A 70-nm gate length CMOS technology for 1.0 V operation has been developed. This technology realizes high performance CMOS roadmap trend and utilizes sub-1 keV ion implantation for source/drain extension formations, quick-cooling RTA process, and ultra-thin gate dielectrics of 1.3 nm. The thickness of the gate dielectrics has been optimized in terms of both the I/sub ON/-I/sub OFF/, tradeoff and gate delay metrics. Obtained I/sub D//sup SAT/ for nMOS and pMOS are 723 /spl mu/A//spl mu/m (I/sub OFF/=16 nA//spl mu/m) and 290 /spl mu/A//spl mu/m (I/sub OFF/=20 nA//spl mu/m), respectively.

UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect

UX6-100 nm generation CMOS integration technology is demonstrated. Various transistor performances (UHP, HP, MP, over-drive), yields of unit processes and 6T-SRAM operation were verified using full-integration processed wafers. To meet the various performance requirements, multi-V/sub TH/, multi-thickness gate-oxide processes and low-leakage gate dielectric are incorporated in the FEOL. To suppress RC increase compared to the previous generation, low-k (k/sub eff/=3.1) interlayer dielectric and Cu dual damascene interconnects are incorporated in the BEOL.

A 500-MHz, 0.4-/spl mu/m CMOS, 32-word by 32-bit 3-port register file

A 0.4-/spl mu/m CMOS, 32-word by 32-bit 3-port register file has been developed for use in high speed microprocessors. It features a high-speed-oriented memory structure, low threshold voltage nMOS FETs, and a short read-precharge design. This register file has been designed for use within a small-skew clock-distribution processor datapath, and experimental results show it to be capable of 500-MHz register file operations.

Suppression of V/sub th/ fluctuation by minimizing transient enhanced diffusion for deep sub-quarter micron MOSFET

It is revealed that the threshold voltage (V/sub th/) fluctuation in deep sub-quarter micron nMOSFETs is due more to variation of channel impurity concentration than to variation of gate length or oxide thickness. This is because the transient enhanced diffusion (TED) of the channel impurity becomes significant when the concentration of the interstitial Si atoms increases as gate length decrease. A rapid thermal annealing process, which minimizes the TED, is very effective in suppressing the V/sub th/ fluctuation.

A 1.5% jitter PLL clock generation system for a 500-MHz RISC processor

We have developed a clock generation system for RISC processors. The system consists of two parts of a PLL, a frequency multiplier, and a phase aligner. The multiplier can multiply the input clock frequency by 2, 4, and 8, and can accomplish a wide frequency range of output clocks, from 60 MHz to 660 MHz. Jitter is reduced to 1.5% of the output clock period by separating the clock generation system into a frequency multiplier and a phase aligner, and by developing a new differential loop filter with high sensitivity phase detection. The phase aligner reduces clock skew between the processor and peripheral LSIs. The system is fabricated with 0.4-/spl mu/m CMOS triple-layer Al process technology and operated at 3.3 V.<<ETX>>

A 400 MHz, 300 mW, 8 kb, CMOS SRAM macro with a current sensing scheme

This paper describes the development of a 400 MHz, 8 kb, 0.4 /spl mu/m CMOS SRAM macro targeted for use in on-chip cache memories. A newly developed pipeline scheme uses a dynamic decoder and half-latches to increase speed by 10% over that of conventional synchronous pipeline SRAMs. Further, a newly developed current sensing scheme, resistant both to noise and to process deviations, contributes to a job reduction in power dissipation.<<ETX>>

Boron Enhanced Diffusion Due to High Energy Ion-Implantation and Its Suppression by Using RTA Process

SIMS measurements revealed that high energy boron-implantation causes transient enhanced diffusion (TED) of a shallow dopant profile due to Si interstitials even for a relatively low dose of {approximately}2E13cm{sup {minus}2}. By systematic analysis, it is found that this anomalous diffusion is most significant in 700--800 C annealing, and it takes place in the initial stage (less than 30 sec for 800 C) of annealing. Moreover, this anomalous diffusion is more considerable than the enhanced diffusion during oxidation (OED) in practical device fabrication processes. It is found that rapid thermal annealing (RTA) at 1,000--1,100 C is effective for suppressing the transient enhanced diffusion and realizing a shallow channel profile for deep sub-micron devices.