Ho-geon Song

A study on wafer level molding for realizing 3-D integration

3D-IC packaging using through silicon via technology has been extensively developed to meet small form factor and low power consumption demands for next generation devices. A wafer molding technology is required for 3D chip integration. Wafer molding is carried out in the chip-to-wafer process to ensure suitable levels of mechanical strength are reached. The key to wafer level mold processing is the reduction of warpage. This paper discusses the material developments and steps taken for process optimization in the wafer molding process to reduce warpage. A 2 chip stack arrangement was used for this investigation, with a 12 inch bottom wafer containing vias, and 9×9 mm top chip wafers. The evaluation was run systematically in three major phases. In the first phase, the levels of warpage experienced during the packaging processes were simulated. The evaluation of three different types of material (Epoxy, Silicone and Hybrid) was carried out in the second phase. The third and final phase involved the testing for warpage at room and high temperature conditions of the epoxy and hybrid based resins. The silicone based resin was also evaluated with varying amounts of filler and adhesion promoter. The modulus and coefficient of thermal expansion (CTE) were found to be extremely important, since lowering this property would result in low warpage levels, both at room and high temperatures, which control the water absorption and temperature cycle reliability in the silicone based resin were established.