Hollie A. Reed

Fabrication of air-channel structures for microfluidic, microelectromechanical, and microelectronic applications

A method is presented for fabricating micro-air-channel structures encapsulated by a dielectric material using a sacrificial polymer based on polynorbornene (PNB) chemistry. A spin-coated film of PNB was patterned to define the exact geometry of the air-channels using conventional lithographic and etching techniques. The sacrificial polymer was encapsulated with a permanent dielectric material. The composite was then raised to elevated temperatures to produce gaseous products which permeate through the encapsulating material (SiO/sub 2/, SiN/sub x/ or other polymer) leaving behind minimal solid residue. Air-channels integrated with metal interconnections can be formed via a Damascene, or in-lay process. After patterning the sacrificial polymer, copper was electroplated, followed by encapsulation with the dielectric. Various issues pertaining to the processing steps have been investigated and are discussed, such as type of encapsulants, feasible air-channel sizes, and processing conditions. Such air-channel structures are believed to have potential applications in microelectronics, displays, printers, multilevel wiring boards, microscale chemical reactors on a chip, and microelectromechanical devices.

Fabrication of microchannels using polycarbonates as sacrificial materials

The use of polycarbonates as thermally decomposable, sacrificial materials for the formation of microchannels is presented. Polycarbonates decompose in the temperature range of 200-300 °C. Two polycarbonates, polyethylene carbonate and polypropylene carbonate, have been used to fabricate microchannels in three different types of encapsulants: an inorganic glass (silicon dioxide), a thermoplastic polymer (Avatrel dielectric polymer) and a thermoset polymer (bisbenzoycyclobutene Cyclotene 3022-57). This paper presents the details of the fabrication process, a thermogravimetric analysis of the sacrificial materials, and the kinetic parameters for the decomposition process. The presence of oxygen or water was found to impact on the decomposition of the sacrificial material. This paper demonstrates the feasibility of forming buried air-cavities in a variety of encapsulants at a modest temperature, thus enabling the use of a wide range of dielectric materials with different thermal stabilities and properties.

Air-channel fabrication for microelectromechanical systems via sacrificial photosensitive polycarbonates

This research involves the fabrication of encapsulated air-channels via acid-catalyzed degradation of photosensitive polycarbonates (PCs). There is a need for lower-temperature, degradable polymeric materials to fabricate buried air-channels for microelectromechanical systems (MEMS), microfluidic devices, and micro-reactors. Some polycarbonates undergo thermolytic degradation in the temperature range of 200 to 350/spl deg/C. These polycarbonates are also known to undergo acid-catalyzed decomposition in the presence of catalytic amounts of acid. A small percentage of an acid in the polycarbonate formulation can greatly reduce the onset of decomposition temperature to the 100 to 180/spl deg/C temperature range. The photoacid and thermal acid induced degradation behavior of PCs and its use as a sacrificial material for the formation of air-gaps have been studied in this work. The decomposition of several polycarbonates with the aid of in situ generated photo-acid has been demonstrated and applied to the fabrication of micro air-channels. Based on FT-IR, mass spectrometry, and thermogravimetric analysis (TGA), a degradation mechanism was proposed.

Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

Sea of Leads (SoL) is an ultrahigh density (>10/sup 4//cm/sup 2/) compliant chip input/output (I/O) interconnection technology. SoL is fabricated at the wafer level to extend the economic benefits of semiconductor front-end and back-end wafer-level batch fabrication to include chip I/O interconnections, packaging, and wafer-level testing and burn-in. This paper discusses the fabrication, the mechanical and electrical performance, and the benefits of SoL. SoL can lead to enhancements in reliability, electrical performance, manufacturing throughput, and cost. A chip with 12 /spl times/ 10/sup 3//cm/sup 2/ compliant I/O leads is demonstrated. The mechanically compliant I/O leads are designed to enable wafer-level testing and eliminate the need for underfill between chips and printed wiring boards by mitigating thermo-mechanical expansion mismatches between the two. The fabrication of partially nonadherent, or slippery, leads is desirable as it allows the leads to freely undergo strain during thermal cycling. Compared to adherent metal leads, preliminary results show that slippery leads enhance the overall in-plane compliance. Microindentation experiments show that a polymer film with embedded air gaps provides substantially higher compliance than a polymer film without embedded air gaps.

Fabrication of microchannels using polynorbornene photosensitive sacrificial materials

© 2003 The Electrochemical Society, Inc. All rights reserved. Except as provided under U.S. copyright law, this work may not be reproduced, resold, distributed, or modified without the express permission of The Electrochemical Society (ECS).

Lithographic Characteristics and Thermal Processing of Photosensitive Sacrificial Materials

Previously, a novel method for fabricating microfluidic and microelectromechanical devices with buried microchannel structures using thermally sacrificial polymers was reported. These previous methods required separate lithographic and etching sequences to pattern the sacrificial polymer. In this work, a more advanced approach in which the sacrificial material is radiation sensitive and can be patterned directly using standard lithographic techniques is explored. The lithographic performance of a new class of photosensitive polynorbornene (PNB) sacrificial materials has been characterized. The effect of soft bake and postexposure bake (PEB) on the cross-linking of photodefinable PNB has also been investigated. It was found that significant cross-linking of PNB occurs after exposure during the subsequent postexposure bake. However, this phenomenon is strongly dependent on the soft bake conditions used in preparing the sample, presumably due to varying levels of residual solvent content. This may he due to the high mass transport of the reactive species because of evaporation of residual solvent and shrinking of polymer matrix during the PEB profess. No noticeable influence of residual solvent on cross-linking has been found during exposure.

Compliant wafer level package (CWLP) with embedded air-gaps for sea of leads (SoL) interconnections

Sea of Leads (SoL) is an ultrahigh I/O density (>10/sup 4/ leads per cm/sup 2/) compliant wafer level package (CWLP) that potentially enables terabit on/off chip electrical bandwidth as well as enhances on-chip high current (e.g. >290 A) distribution of a mixed-signal system-on-a-chip (SoC). The addition of embedded air-gaps may mitigate problems with thermal expansion between the chip and printed wiring board, increase effective compliance of the package for wafer level testing applications, and reduce the dielectric constant of the interconnect dielectric material. An SoL package with 12000/cm/sup 2/ leads has been designed and fabricated, along with a prototype SoL package with 1000/cm/sup 2/ leads on top of a dielectric layer containing embedded air-gaps.

Optical waveguides with embedded air-gap cladding integrated within a sea-of-leads (SoL) wafer-level package

Optical waveguides are integrated into a Sea-of-Leads (SoL) wafer-level package. A photosensitive polycarbonate composite is incorporated to provide a buried air-gap cladding that allows a refractive index contrast, /spl Delta/n, between waveguide core and cladding regions of /spl Delta/n = 0.52. The final package contains 1000 electrical input/output (I/O) interconnects and 32 large-area optical waveguides for electrical chip-to-chip and optical intra-chip clock or data interconnection, respectively. Monolithic fabrication of passive optical interconnect components is described.

Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection

Sea of leads (SoL) is a novel ultra-high-density compliant wafer-level packaging technology. The x-y-z compliant input/output (I/O) leads are batch fabricated by simply extending wafer-level batch fabrication of on-chip multilevel interconnect networks. Two-port microwave measurements reveal that the leads exhibit an insertion-loss of less than 0.4dB in the 0.1-45GHz frequency range. In addition, worst-case insertion-loss of signal propagation into and out of the package is 1.15dB at 45GHz. Because the compliant leads are short, their electrical parasitics are minimal. A mixed-signal system-on-a-chip (SoC) requires packages that are compatible with optical interconnect technology. Physical design rules describing SoL design compatibility with board-level optical signal distribution via waveguides are derived.

Fabrication of microchannels for compliant wafer level packaging using sacrificial materials

Electronic packaging and chip-to-module connections have evolved to meet the needs of electronic systems. The rate of change of the technology will accelerate as the package disappears and optical interconnects come into play. Compliant wafer-scale packaging is an approach which can be used to provide acceptable electrical and mechanical functions for future electronic packaging. In this work, buried air-cavities using sacrificial polymers are used to provide compressible input/output leads.