Kevin P. Martin

Interconnect opportunities for gigascale integration

Throughout the past four decades, semiconductor technology has advanced at exponential rates in both productivity and performance. In recent years, multilevel interconnect networks have become the primary limit on the productivity, performance, energy dissipation, and signal integrity of gigascale integration. Consequently, a broad spectrum of novel solutions to the multifaceted interconnect problem must be explored. Here we review recent salient results of this exploration. Based upon prediction of the complete stochastic signal interconnect length distribution of a megacell, optimal reverse scaling of each pair of wiring levels provides a prime opportunity to minimize cell area, clock period, power dissipation, or number of wiring levels. Using a heterogeneous version of Rents rule, a design methodology for the global signal, clock, and power/ground distribution networks for a system-on-a-chip has been derived. Wiring area, bandwidth, and signal integrity are the prime constraints on the design of the networks. Three-dimensional integration offers the opportunity to reduce the length of the longest global interconnects in a distribution by as much as 75%. Wafer-level batch fabrication of chip input/output interconnects and chip scale packages provides new benefits such as I/O bandwidth enhancement, simultaneous switching-noise reduction, and lower cost of packaging and testing. Microphotonic interconnects have long-term potential to reduce latency, power dissipation, and crosstalk while increasing bandwidth.

Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

Sea of Leads (SoL) is an ultrahigh density (>10/sup 4//cm/sup 2/) compliant chip input/output (I/O) interconnection technology. SoL is fabricated at the wafer level to extend the economic benefits of semiconductor front-end and back-end wafer-level batch fabrication to include chip I/O interconnections, packaging, and wafer-level testing and burn-in. This paper discusses the fabrication, the mechanical and electrical performance, and the benefits of SoL. SoL can lead to enhancements in reliability, electrical performance, manufacturing throughput, and cost. A chip with 12 /spl times/ 10/sup 3//cm/sup 2/ compliant I/O leads is demonstrated. The mechanically compliant I/O leads are designed to enable wafer-level testing and eliminate the need for underfill between chips and printed wiring boards by mitigating thermo-mechanical expansion mismatches between the two. The fabrication of partially nonadherent, or slippery, leads is desirable as it allows the leads to freely undergo strain during thermal cycling. Compared to adherent metal leads, preliminary results show that slippery leads enhance the overall in-plane compliance. Microindentation experiments show that a polymer film with embedded air gaps provides substantially higher compliance than a polymer film without embedded air gaps.

Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections

An electrical-optical chip input-output (I/O) interconnection technology called sea of polymer pillars (SoPP) is presented. SoPP provides highly process-integrated and mechanically flexible (compliant) electrical-optical die-to-board interconnections that mitigate thermo-mechanical expansion mismatches. The I/O density of SoPP exceeds 10/sup 5//cm/sup 2/. The compliance of the polymer pillars is shown to be 3-5 /spl mu/m/mN. Approximately 50% input optical coupling efficiency into a volume grating coupler through a set of polymer pillars is demonstrated.

Interconnecting device opportunities for gigascale integration (GSI)

In recent years interconnecting devices have become primary limits on the performance, energy dissipation, signal integrity, and productivity of gigascale integration (GSI). Opportunities to address the interconnect problem include new materials and processes, reverse scaling, novel microarchitectures, three-dimensional integration, input/output interconnect enhancements, RF wireless interconnects and microphotonics.

Low energy electron‐enhanced etching of Si(100) in hydrogen/helium direct‐current plasma

Low energy electron‐enhanced etching of Si(100) has been achieved by placing the sample on the anode of a dc discharge in hydrogen/helium mixtures. Over a broad range of gas composition, gas pressure, and discharge current, nonpatterned samples gave etch yields of 0.01–0.02 atoms/electron, and average etch rates of 2000–3000 A/min. Postetch examination by atomic force microscopy revealed surface roughness of 2–3 nm. These results are related to incident flux of H atoms and electrons through a simple model of the anode sheath layer above the sample.

Process optimization and proximity effect correction for gray scale e-beam lithography

Three-dimensional microstructures find applications in diffractive optical elements, photonic elements, etc., and can be efficiently fabricated by e-beam lithography. Good process control and efficient proximity effect correction are important for achieving the desired structures. With polymethylmethacrylate as the resist, a process optimization of different develop conditions is carried out to identify a process that is most conductive to gray scale features. A novel proximity effect correction scheme called effective dose-depth (EDD) method is proposed. Using the EDD method for grating design and the optimized process, blazed gratings have been fabricated with excellent uniformity and low surface roughness.

THE DRY ETCHING OF GROUP III-NITRIDE WIDE-BANDGAP SEMICONDUCTORS

Fabricating device structures from the III-N semiconductors requires dry-etching processes that leave smooth surfaces with stoichiometric composition after transferring patterns with vertical sidewalls. Results obtained by standard methods are summarized, and the extent of concomitant ion bombardment damage is assessed. A new low-damage technique—low-energy electron- enhanced etching—that avoids ion bombardment altogether is described, and early results for III-N materials are summarized. Etching issues critical in forming contacts and fabricating laser facets and mirrors are highlighted, and some prospects for future work are also identified.

Low energy electron‐enhanced etching of GaAs(100) in a chlorine/hydrogen dc plasma

Low energy electron‐enhanced etching of GaAs(100) has been achieved by placing the sample on the anode of a low‐pressure hydrogen/chlorine dc discharge. Samples etched at room temperature reveal good anisotropy (≳20), good selectivity (≳200 against SiO2 masks at room temperature), and smooth surfaces at etch rates of 250 A/min; etch rates up to 4.5 μm/min were achieved at 150 °C. The dependence of the etch characteristics on gas composition, pressure, and temperature is described.

Sea of leads: a disruptive paradigm for a system-on-a-chip (SoC)

The authors show that Sea of leads (SoL) is a disruptive paradigm for system-on-a-chip (SoC) because it intends to use wafer-level batch fabrication of ultra high density (>10/sup 4//cm/sup 2/) x-y-z compliant input/output leads and packages as well as wafer level DC/AC testing and burn-in to enhance performance, cost, size, weight, and reliability of a mixed signal SoC.

Sea of dual mode polymer pillar I/O interconnections for gigascale integration

The Sea of Polymer Pillars offers highly compliant electrical, optical, and RF wafer-level I/O interconnects at an I/O density larger than 10/sup 5//cm/sup 2/. Dual mode I/O pillars function simultaneously as both electrical and optical interconnects to offer circuit/system designers essentially unlimited I/O bandwidth at potentially the lowest cost.