Hongil Yoon

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor

To verify three important circuit schemes suitable for DRAMs in mobile applications, a 1.8-V 128-Mb SDRAM was implemented with a 0.15-/spl mu/m technology. To achieve an ideal 33% efficiency, the double boosting pump uses two capacitors series connection at pumping phase, while they are precharged in parallel. The hybrid folded current sense amplifier together with a novel replica inverter connection improved power and speed performances. Also, a dual-referenced adjustment scheme for a temperature sensor was proposed to allow a very high accuracy in tuning. Without loss in productivity, the implemented dual-referenced searching technique achieved tuning error of less than /spl plusmn/2.5/spl deg/C.

Low-voltage, high-speed circuit designs for gigabit DRAMs

This paper describes several new circuit design techniques for low V/sub CC/ regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (/spl Delta/V/sub BL/) as well as the V/sub GS/ margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-/spl mu/m twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t/sub RAC/) of 28 ns at V/sub cc/=1.5 V and T=25/spl deg/C has been obtained.

A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture

A 1.8 V 4 Gb DDR SDRAM for low voltage and high speed at full density has reduced inter-bitline coupling noise in the twisted open bit line architecture. Amplifier sensitivity and sensing margin are improved by gain-controlled pre-sensing and active calibration of the bitline reference voltage. For noise-immune power-stabilized operation, three circuit schemes suitable for the SDRAM are presented: (i) twisted open bitline (TOB) architecture; (ii) gain-controlled pre-sensing (GCP); and (iii) reference bitline calibration (RBC). The TOB scheme eliminates the coupling noise between adjacent BLs by holding neighboring bitlines stable at the reference voltage with the open readout and sensing using a reference BL from the adjacent block. The GCP scheme increases the sensing margin and speed by employing transconductance-matched pre-amplification. The RBC scheme actively mimics the cell data retention characteristics and yields an optimal voltage level for the reference BL from the charge-shared voltage from replica BL pairs. Together with a chip-size-efficient core signal repeating architecture, these schemes ensure reliable low-voltage and high-speed cell and core operation.

Performance characteristics of SOI DRAM for low-power application

Process integration of cell capacitors that can circumvent the usual difficulties of large topographic height difference and high-temperature process are presented. A 16 Mbit silicon-on-insulator (SOI) DRAM with a 0.3 /spl mu/m design rule is successfully fabricated and analyzed for processing integrity and circuit performance based on process integration of the cell capacitor using the pattern-bonded SOI (PBSOI) technology. Measurements for the strobe access time (tRAC) acid the operation current (I/sub ccl/) show significant improvement (over 25%) for the SOI DRAM compared to those for the 16 Mbit bulk counterpart with the same circuit and layout. On the transistor side, ultra-low-voltage transistor technology using the body bias control schemes is also implemented and investigated. Devices with small leakage current and almost ideal subthreshold swing are obtained. The results give us guidance for transistor and process schematics for low-voltage DRAM application.

A 2.5 V 333 Mb/s/pin 1 Gb double data rate SDRAM

While on-chip data flight times approach a few tens of nanoseconds for gigabit-scale DRAMs, a bandwidth over 250 MHz requires data input and output timing accuracy within 0.3 ns. Although a high-speed data interface can be achieved using precise clock generators such as delay locked loop (DLL), skews due to a long data access path may cause loss of internal timing margins. Diminished timing margin may be detrimental to wave pipelining for high-bandwidth. This 1 Gb double data rate (DDR) SDRAM featuring ODIC chip with nonODIC package (OCNOP), cycle-time-adaptive wave pipelining (CTAWP), and variable stage analog DLL achieves high performance despite stringent processing variations in 0.14 /spl mu/m design rules.

Double boosting pump, hybrid current sense amplifier, and binary weighted temperature sensor adjustment schemes for 1.8V 128Mb mobile DRAMs

A 1.8V 128Mb SDRAM is implemented for low current mobile applications with a 0.15/spl mu/m technology. The double boosting pump and hybrid current sense amplifier schemes are optimized for the low voltage regime with high pumping efficiency and stable I-to-V gain, respectively. A temperature sensor together with the binary weighted adjustment technique allow a very accurate implementation without loss in productivity.