Hormoz Djahanshahi

Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications

This paper describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. Fully differential CMOS circuits are presented for an integrated physical layer controller of a 622-Mb/s (OC-12) system, although the design can be used in other systems with clock speeds in the 622-933-MHz range. Simulations and experimental results are presented for the building blocks including novel designs for a current-controlled oscillator (CCO) and a differential charge pump. The CCO is based on a two-stage ring oscillator. It consists of parallel differential amplifier pairs which reliably generate the necessary phase shift and gain to fulfill the oscillation conditions over process and temperature variations. Two test chips are implemented in 0.35-/spl mu/m CMOS. One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external loop filter, can be used for flexible testing and CDR applications. The other chip is a monolithic CDR with integrated loop filter. It exhibits a power consumption of 0.2 W and a measured rms clock jitter of 12.5 ps at 933 MHz.

A fully integrated tri-band, MIMO transceiver RFIC for 802.16e

A 0.18-mum CMOS tri-band MIMO transceiver for fixed and mobile WiMAX applications is presented. The transceiver supports operation in the 2.3-2.7 GHz, 3.3-3.8 GHz, or 4.9-5.95 GHz bands. A novel DC-offset removal scheme is used to enable a low-cost direct-conversion architecture. The transmitter exhibits an EVM of -38 dB, -36 dB, and -33 dB @ 0 dBm output power for the 2G, 3G, and 5G bands respectively. In full MIMO operation at 3.5 GHz, the TX dissipates 402 mW and 450 mW in RX mode.

Modeling and characterization of VCOs with MOS varactors for RF transceivers

As more broadband wireless standards are introduced and ratified, the complexity of wireless communication systems increases, which necessitates extra care and vigilance in their design. In this paper, various aspects of popular voltage-controlled oscillators (VCOs) as key components in RF transceivers are discussed. The importance of phase noise of these key blocks in the overall performance of RF transceivers is highlighted. Varactors are identified as an important component of LC-based oscillators. A new model for accumulation-mode MOS varactors is introduced. The model is experimentally verified through measurements on LC-based VCOs designed in a standardm CMOS process.

On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise

Frequency synthesis at mm-wave range suffers from a severe tradeoff between phase noise (PN) and frequency tuning range (FTR). This work presents the analysis and compares the performance of fundamental-mode voltage-controlled oscillators (F-VCOs) to harmonic-mode VCOs (H-VCOs). It is shown that unlike a mm-wave F-VCO, an H-VCO can simultaneously achieve higher FTR and lower PN. An H-VCO architecture, denoted as self-mixing VCO (SMV), is presented where the VCO core generates both the first (fο) and second harmonic (2fο) and then mixes them together to obtain the desired mm-wave third-harmonic (3fο). Use of a Class-C push-push topology as the VCO core enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance, and improves PN. Compared to an F-VCO operating in a mm-wave band at a fundamental frequency that equals 3fο, the proposed SMV architecture achieves about 2× higher FTR and a better PN performance. A 52.8-62.5 GHz SMV prototype is designed and implemented in a 0.13 μm CMOS process. Measurement results show that the VCO achieves an FTR of 16.8% with a PN of -100.6 dBc/Hz at 1 MHz offset-resulting in an FTR-inclusive figure-of-merit (FoMT) of -190.85 dBc/Hz while consuming 7.6 mW from a 1.2 V supply.

Characterization and modeling of accumulation-mode MOS varactors

The characterization and modeling of an accumulation-mode MOS varactor implemented in a standard 0.13 mum CMOS process is discussed. An experimental model based on the physical parameters of the device is verified. The model has been extracted, using S-parameter measurements, from different MOS varactor structures and is valid in both accumulation and depletion regions. The model has been verified both directly using the extracted values and indirectly by comparing the measured and simulated tuning curves of 5-6 GHz voltage controlled oscillators designed in the same process

Modeling of MOS varactors and characterizing the tuning curve of a 5-6 GHz LC VCO

A novel accumulation-mode MOS varactor model used for characterizing the tuning curve of LC-tank voltage-controlled oscillators (VCOs) is presented. The VCO tuning characteristic is seen to depend not only on the C-V characteristics of the varactor but also on losses in the tank. Effects of variations in the tank quality factor (Q) and oscillators swing on the VCO tuning curve are discussed. Also a practical SPICE model using a pMOS transistor to describe an accumulation-mode MOS varactor is proposed. The model has been verified in a number of structures manufactured in a standard 0.13 /spl mu/m CMOS process and is suitable for simulation within many circuit design environments.

Design and verification of integrated inductors in CMOS

The design and verification of several monolithic inductor structures is presented. Based on the measurement results of proof-of-concept prototypes in 65 nm CMOS, the inductance (L) and quality factor (Q) of these structures are analyzed both qualitatively and quantitatively. Also, a closed-form approximation for the inductance of vertical spirals is presented and the results are applied to design a compact inductor for serie-speaking at the input of an impedance-matched amplifier.

A 27-GHz low-power push-push LC VCO with wide tuning range in 65nm CMOS

Push-push voltage-controlled oscillators (VCOs) achieve high oscillation frequencies by relying on the boosted second harmonic component of the oscillator. These VCOs however, typically require a high power to deliver a reasonable output swing. In this paper, we first derive an analytical expression that relates the amplitude of the second harmonic of an LC VCO to the C-V characteristics of its varactor. Then based on the results of the analysis, we present the design of a low-power and compact 27-GHz push-push VCO in 65 nm CMOS that exhibits a 28.5% tuning range while consuming 21 mW (including buffers) from a 1 V supply. At 27-GHz output, the VCO achieves a phase noise of −101 dBc/Hz at 1-MHz offset.

Low-Jitter 0.1-to-5.8 GHz clock synthesizer for area-efficient per-port integration

Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst them, which can compromise their superior jitter performance. This paper presents an analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner. Based on this study, a low-jitter highly packable clock synthesizer unit (CSU) supporting a continuous (gapless) frequency range up to 5.8GHz is designed and implemented in a 65 nm digital CMOS process. Measurement results are presented for densely integrated CSUs within a multirate multiprotocol system-on-chip PHY device.