Amir Hossein Masnadi Shirazi

On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise

Frequency synthesis at mm-wave range suffers from a severe tradeoff between phase noise (PN) and frequency tuning range (FTR). This work presents the analysis and compares the performance of fundamental-mode voltage-controlled oscillators (F-VCOs) to harmonic-mode VCOs (H-VCOs). It is shown that unlike a mm-wave F-VCO, an H-VCO can simultaneously achieve higher FTR and lower PN. An H-VCO architecture, denoted as self-mixing VCO (SMV), is presented where the VCO core generates both the first (fο) and second harmonic (2fο) and then mixes them together to obtain the desired mm-wave third-harmonic (3fο). Use of a Class-C push-push topology as the VCO core enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance, and improves PN. Compared to an F-VCO operating in a mm-wave band at a fundamental frequency that equals 3fο, the proposed SMV architecture achieves about 2× higher FTR and a better PN performance. A 52.8-62.5 GHz SMV prototype is designed and implemented in a 0.13 μm CMOS process. Measurement results show that the VCO achieves an FTR of 16.8% with a PN of -100.6 dBc/Hz at 1 MHz offset-resulting in an FTR-inclusive figure-of-merit (FoMT) of -190.85 dBc/Hz while consuming 7.6 mW from a 1.2 V supply.

On the use of body biasing to improve linearity in low LO-power CMOS active mixers

In a radio-frequency (RF) transceiver, the linearity of the mixer has a profound effect on the overall transceiver performance. In many RF transceivers, active mixers are used due to their higher gain which also improves the overall receiver noise figure. In a typical RF active mixer where the transistors in the LO stage switch abruptly, most of the nonlinear distortions come from the transconductance or RF stage and thus the linearity of the mixer can be enhanced by proper design of the RF stage. In low-power receivers, however, to reduce the power consumption of the local oscillator (LO) circuit, the amplitude of LO signal is low and thus the switching of the transistors in the LO stage of the mixer is gradual. In this paper, we propose a technique to improve the linearity of such low-power mixers by enhancing the linearity of the LO stage. In particular, body biasing is utilized in the LO stage to improve the linearity. To verify the effectiveness of the proposed technique, two proof-of-concept double-balanced down-conversion active mixers have been designed and fabricated in 0.13-@?m CMOS. The maximum IIP3 of +2.7dBm and -4.9dBm at a conversion gain of 13dB and 16dB are achieved for the first and second prototype respectively. For a 2.4GHz RF input signal and an intermediate-Frequency (IF) of 50MHz, the first prototype consumes 2.4mW from a 1.2V supply while the second one consumes only 780@?W from a 0.7V supply.

An ultra-low-voltage CMOS mixer using switched-transconductance, current-reuse and dynamic-threshold-voltage gain-boosting techniques

In this paper, an architecture for ultra-low-voltage radio-frequency (RF) CMOS mixers is introduced. The structure uses switched-transconductance technique in conjunction with current-reuse and dynamic-threshold-voltage gain-boosting techniques to reduce the required supply voltage and power consumption while providing a high conversion gain. As a proof-of-concept, a 2.5-GHz down-conversion mixer is designed and laid out in a 0.13-μm CMOS process. Post-layout simulation results show that the mixer achieves a conversion gain of 13 dB, double-side-band (DSB) noise figure (NF) of 12.7 dB and input-referred third-order intercept point (IIP3) of -3.08 dB while consuming 480 μW from a 0.35-V supply.

A Class-C self-mixing-VCO architecture with high tuning-range and low phase-noise for mm-wave applications

Achieving high tuning-range and low phase-noise simultaneously in mm-wave voltage-controlled oscillators (VCO) has been a severe design challenge. Our architecture, referred herein as a self-mixing VCO (SMV), utilizes a Class-C push-push VCO topology to generate the first (f0) and second harmonics (2f0) and then mixes them together to obtain the desired third harmonic (3f0) component. Compared to a fundamental-mode VCO operating at 3f0 in mm-wave band, the SMV architecture achieves superior frequency tuning range (FTR) and phase-noise (PN) performance. A Class-C topology enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance and reduces phase noise. A 52.8-to-62.5 GHz SMV prototype is designed and implemented in a 0.13-μm CMOS process. Measurement results show an FTR of 16.8% together with a PN of -100.57 dBc/Hz at 1 MHz offset - resulting in an FTR-inclusive figure-of-merit (FOMT) of -190.85 dBc/Hz while consuming 7.6 mW from a 1.2 V supply voltage.

Improving linearity of CMOS Gilbert-cell mixers using body biasing

This paper presents the application of body biasing to improve linearity performance of CMOS Gilbert-cell mixers. In order to improve the linearity, the bulk bias voltage of the transistors in the local oscillator (LO) stage is adjusted. The improvement in linearity is obtained while the conversion gain and power consumption of the mixer remain virtually intact. A 0.13-μm CMOS proof-of-concept prototype is implemented which operates at radio frequency (RF) of 2.4 GHz with an intermediate frequency (IF) of 50 MHz and draws 2.25 mA from a 1.2-V supply. Based on post-layout simulations, the proposed technique results in a 5-dB improvement in the input-referred third-order intercept point (IIP3) of the prototype mixer.

A quad-core-coupled triple-push 295-to-301 GHz source with 1.25 mW peak output power in 65nm CMOS using slow-wave effect

Achieving high output power in (sub-)THz voltage-controlled oscillators (VCOs) has been a severe design challenge in CMOS technology. In this work, an architecture for coupled terahertz (THz) VCOs is presented. The architecture utilizes four coupled triple-push VCOs and combines the generated third harmonic currents using slow-wave coplanar waveguide (S-CPW) at 300 GHz. Coupling four cores increases output power, and use of S-CPW reduces the loss and increases the quality factor of the VCO tank. It is shown that using S-CPW results in ~2.6 dB of lower loss as compared to the conventional CPW or grounded-CPW (GCPW) structures. The VCO is tuned using parasitic tuning technique and achieves 1.7% frequency tuning range (FTR). The proposed structure is designed and fabricated in a 65-nm bulk CMOS process. The measured peak output power of the 295-to-301 GHz VCO is 0.9 dBm (≈1.25 mW) at 300 GHz while consuming 235 mW (with a DC to RF efficiency of 0.52%).

A dual-tank LC VCO topology approaching towards the maximum thermodynamically-achievable oscillator FoM

There exists a fundamental limit in improving the phase noise performance of LC-tank oscillators. Impediments to reach this limit are first discussed, and then a clipping LC VCO topology based on dual tank is presented to mitigate them. This topology can approach within 3 dB of the maximum thermodynamically achievable figure-of-merit (FoM) limit. Compared to conventional class-B/C/D/F oscillators, it is capable of reducing both close-in and far-out phase noise. As a proof of concept, a prototype 4.17-4.95 GHz VCO in a 0.13-μm CMOS process achieves a phase noise of -97 and -143 dBc/Hz at 30 kHz and 3 MHz offset, respectively.

A low-power DC-to-27-GHz transimpedance amplifier in 0.13-µm CMOS using inductive-peaking and current-reuse techniques

The growing demand for high-speed communication necessitates high-data-rate and power-efficient integrated optical link solutions. In this paper, a power-efficient CMOS transimpedance amplifier (TIA) is proposed which uses current-reuse and inductive-peaking techniques to achieve a wide bandwidth, a low input impedance, and a high gain. As a proof-of-concept, a DC-to-27-GHz TIA is designed and laid out in a 0.13-μm CMOS process. Post-layout simulation results show that in the presence of a photo diode with a capacitance as large as 500 fF, the TIA achieves a 3-dB bandwidth of 27.3 GHz and a gain of 50 dBΩ while consuming 14.3 mW from a 1.2-V supply.

A 219-to-231 GHz Frequency-Multiplier-Based VCO With ~3% Peak DC-to-RF Efficiency in 65-nm CMOS

Signal sources at mm-wave and (sub-)terahertz frequencies in CMOS can be classified into two broad categories: harmonic oscillators and oscillators that are based on the frequency multiplication of fundamental sources. This paper shows that frequency-multiplier-based sources potentially have a higher dc-to-RF efficiency than do the popular harmonic oscillators in 65-nm CMOS. To improve the power efficiency of CMOS signal sources that operate near or above the cutoff frequency of the device, design factors including the harmonic current efficiency, the effective output conductance, and the passive losses should be carefully tailored. An architecture is proposed in which: 1) the core voltage-controlled oscillator is optimized to efficiently generate a strong fundamental harmonic; 2) separate class-C frequency doublers are utilized to decouple fundamental signal generation and harmonic extraction and to reduce conductance loss; and 3) doubler circuits are separately optimized to simplify the output matching and power combining network, and hence avoid long and lossy transmission lines. A circuit prototype shows a measured peak output power and dc-to-RF efficiency of 3 dBm and 2.95%, respectively.

A full-duplex receiver with 80MHz bandwidth self-interference cancellation circuit using baseband Hilbert transform equalization

To enable simultaneous full-duplex radios, self-interference (SI) cancellation (SIC) circuits that attain large cancellation bandwidths (BWs) are needed to support modern standards such as Long-Term Evolution (LTE). For mobile applications, SIC should be linear, tunable, fully monolithic (compact form factor) and must be implemented at the radio-frequency (RF) front-end. Emulating the group delay (GD) and complex impedance of the SI channel, an SIC circuit is proposed that achieves an 80 MHz of SIC BW using just a single tap delay. GD is estimated using frequency translations and baseband (BB) low pass filtering, and complex impedance is emulated using a vector modulator (VM). We prove that the combination of GD and VM results in a time-domain Hilbert transform equalization (HTE), enabling broadband cancellation and reducing the number of GD taps needed, thereby saving area. Implementing HTE at BB using passive circuits further reduces area, power consumption and maintains linearity. A prototype in 0.13-µm CMOS process occupies 0.4 mm2 and attains 23 dB of SIC measured over an 80-MHz signal BW, while consuming 13 mW. Total power and area including the receiver is 64.4 mW and 0.72mm2, respectively.