Hosam Haggag

Test time reduction of successive approximation register A/D converter by selective code measurement

This paper proposes a novel methodology for reducing the static linearity test time of SAR A/D converters. Due to the low data conversion rate and high resolution, the test time required measuring the linearity specifications such as INL and DNL in SAR A/D converters can be as high as 40% of the total A/D converter test time. The proposed method is based on the fact that the non-idealities in the code widths of the converter are correlated to and are dominated by the manufacturing variations in specific components used in the A/D converter design. Therefore, by measuring a subset of the total set of code widths that are directly affected by manufacturing variations in these components, all the code widths are estimated accurately. As opposed to prior work, the proposed approach does not use linear error models and describes a method which directly measures the code widths using a piecewise linear ramp designed to extract test information accurately from the relevant codes. The proposed method has been applied to a SAR A/D converter in production with achieved test time reduction of more than 75%

Cmos built-in test architecture for high-speed jitter measurement

A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - I GHz input range with resolution of 70ps RMS jitter occupying 0.05 75mmz area.

Testing of Precision DACs Using Low-Resolution ADCs with Dithering

The bottleneck of DAC testing is the fast and accurate measurement devices. Production testing of high-resolution DACs with gigahertz clock rates is a challenging problem, and there is no widely adopted approach for on-chip testing of precision DACs in an SoC system. This work presents a new approach for testing high-resolution DACs. High speed data acquisition is achieved with flash ADCs; sufficient resolution is provided by dithering; and high test accuracy is guaranteed by the proposed data processing algorithm. This method provides a potential solution to both the production and on-chip DAC testing problems. Simulation results show that the static linearity of 14 bit DACs can be tested to better than 1 LSB accuracy, and dynamic performance of more than 85 dB SFDR can be tested with 1 dB accuracy, using 6-bit ADCs and dithering. Experimental results included in the paper also affirm the performance of the algorithm in testing high-resolution DACs using 6-bit ADCs

NOR virtual ground (NVG)-a new scaling concept for very high density flash EEPROM and its implementation in a 0.5 um process

A new NOR virtual ground flash cell array concept is introduced. A 2.4 um/sup 2/ cell size based on a 0.5 um process is realized, which is a 35% cell size reduction compared with the conventional NOR cell.<<ETX>>

Testing of Precision DAC Using Low-Resolution ADC With Wobbling

Testing of high-resolution, digital-to-analog converters (DACs) with gigahertz clock rates is a challenging problem. The bottleneck is fast and accurate output measurement. This paper presents a novel high-performance DAC testing approach that uses a flash analog-to-digital converter (ADC) to achieve highspeed data acquisition, adopts the wobbling technique to provide a sufficient resolution, and processes the data with a sophisticated algorithm to guarantee high test accuracy. Simulation results show that, by using a 6-bit ADC and wobbling, the static linearity of 14-bit DACs can be tested to better than 1-LSB accuracy. The experimental results that are included in the paper also affirm the performance of the algorithm. This method provides a solution to both the production and on-chip testing problems of high-performance DACs.

Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement

Timing measurements for gigahertz clock frequencies require high accuracy and resolution. This paper proposes a scalable built-in self-test (BIST) method that measures accumulated period jitter over a programmable number of periods, without using another reference clock. This on-chip method uses a charge pump to convert time to a voltage, which is digitized by an all-digital flash analog-to-digital converter (ADC). The ADC employs multiple chains of inverter strings composed of three series inverters instead of the popular analog comparators. The inverter thresholds set the reference voltages for triggering given an input dc value. The output is calibrated and converted to jitter measurement. The design using a 0.25 /spl mu/m BiCMOS process, with an input range of 625 MHz-1 GHz, shows that a resolution of 70 ps root mean square (rms) jitter can be achieved, while occupying 0.0575 mm/sup 2/ area with a very conservative layout style. The design has been fabricated and tested, and the test results are presented.

Experimental results for high-speed jitter measurement technique

A BIST method to measure jitter without external references is presented. Measured data from 0.25- m BiCMOS chips show jitter resolution about 30 to 50 ps over 8 cycles of a 1 GHz input signal. The measurement technique uses the clock signal under test to control the charging of the input capacitance of an ADC. One advantage of this design is that it does not require an external jitter-free reference clock or a voltage reference. Design improvements from architectures to circuits are discussed and the method has potentials in other timing measurement applications.

A new erase VT distribution model for reliability design in high density flash EEPROM

This paper describes an improved analytical F-N channel erase and V/sub T/ distribution model by including both process and cell parameters. This model is also able to predict the tightening of V/sub T/ distribution after using F-N soft reprogramming techniques. The accuracy of the model is verified by measured V/sub T/ curves and distribution. This new model provides a simple and useful tool for cell optimization and reliability design-in by accurately correlating V/sub TE/ distribution to physical parameters of process and memory cell.

A new cell and process for very high density full feature EEPROMs and low power applications

A novel high density full feature EEPROM cell with minimum process complexity is proposed. The new structure is a contactless cell with buried N+ bit lines. The floating gate is self aligned to the word line, using self aligned stacked etch technology. Strong reduction of contacts number and cell area is achieved with respect to the conventional Flotox cells. Electrical characteristics and reliability behaviour of this novel structure have been studied and are reported together with the fabrication process. Performances and scalability make this cell interesting for future low power multi-megabit EEPROM applications.<<ETX>>

Decision tree based mismatch diagnosis in analog circuits

Mismatch is a critical consideration in analog circuit design. Knowledge of mismatch locations and an understanding of their impact on circuit performance are crucial for design optimization and process improvement. We present a circuit level mismatch diagnosis methodology in this paper. The functional parameters with abnormal values are measured as manifestations of mismatch, from which reverse tracing is employed to determine the mismatch source. The methodology is implemented on a representative benchmark and its efficiency confirmed by simulation results