Howard C. Yang

Current-feedthrough effects and cancellation techniques in switched-current circuits

Distortion due to device mismatches and clock-feedthrough in switched-current circuits is analyzed. A replication-based current feedthrough cancellation technique that reduces the clock-feedthrough current more than 20 dB is proposed. SPICE simulation results for this circuit are given.<<ETX>>

An active-feedback cascode current source

An MOS cascode current source that employs both active and passive series feedback is reported. Small-signal analysis and SPICE simulation results show that a CMOS implementation of the active-feedback cascode current source provides an output open-circuit Thevinin voltage greater than 10/sup 6/ V. This represents an increase of about two orders of magnitude as compared with the conventional cascode current source. The active-feedback cascode current source maintains the same output voltage swing range as the conventional double cascode. >

Current-mode logic techniques for CMOS mixed-mode ASICs

Current-steering logic (CSL) has been developed especially for high-precision, high-speed, mixed-mode application-specific integrated circuits (ASICs). Using simple CMOS circuitry reminiscent of bipolar integrated injection logic, the logic levels of a CSL gate are realized in the current domain by steering a constant DC bias current. Internal voltage swings are typically less than one volt. Consequently, measured power supply (V/sub dd/) current spikes are typically only 15 mu A for a CSL inverter implemented in a 2- mu m p-well CMOS technology, a reduction of two orders of magnitude compared to the 1.5-mA current spikes typical of a conventional static CMOS inverter. The reduction in digital switching noise allows the development of higher performance on-chip analog circuitry in CMOS mixed-mode applications minimum measured propagation delay is about 500 ps with a power-delay product of 0.35 pJ.<<ETX>>

An integrated CMOS mixed-mode signal processor for disk drive read channel applications

A read channel processor architecture for Winchester disk drive applications is presented, designed to operate with data rates from 10 to 32 Mbits/sec with (1,7) Run Length Limited (RLL) encoding on a 5 volt 1-/spl mu/m CMOS technology. The processor performs the functions of pulse detection and data separation using integrated CMOS analog amplifiers and filters and a digital phase-locked loop (PLL). It integrates many of the functions previously performed with discrete components and has enhanced programmability to more fully support Zoned Bit Recording (ZBR). This paper presents an architectural overview of the processor with comparisons to existing solutions, detailing the system constraints of the architecture. Unique CMOS circuit designs are presented along with the pipelined architecture of the digital PLL. >

Small-signal analysis and minimum settling time design of a one-stage folded-cascode CMOS operational amplifier

A small-signal analysis of the single-ended one-stage folded-cascode CMOS operational amplifier is presented. The analysis results in a four-pole two-zero representation from which a two-pole model is extracted that is sufficiently accurate for many applications in switched-capacitor (SC) circuits. A design equation for obtaining the minimum settling time (MST) response for SC applications is given. >

An equivalent circuit model for two-stage operational amplifiers

The two-pole equivalent-circuit model for frequency compensation has been improved to provide more accurate unity-gain phase margin calculations for a two-stage operational amplifier when the second-stage pole is dominant. The increased accuracy allows for minimum settling time compensation, which gives maximum speed in switched-capacitor circuit applications. The model also clarifies some confusion that has existed previously regarding pole-splitting compensation. SPICE2 simulations were used to verify the improved equivalent circuit model.<<ETX>>

A high speed digital data separator design using real time DSP for disk drive applications

A salient digital data separator architecture using a digital phase-locked loop (PLL) based on high-speed digital filters for disk drives with constant density recording is described. In read mode this data separator performs clock recovery, data synchronizationf, sync field search and detect, address mark detect, and data decoding from

GaAs buried-channel MESFET analog integrated circuits

GaAs analog integrated circuits have been implemented using a buried-channel MESFET technology. The circuits exhibit higher precision than similar realizations in conventional technology because the frequency dependence of the small-signal parameters is reduced greatly. Higher speed is also achieved since the buried-channel structure allows for 0.25- mu m minimum gate lengths, whereas 0.5- mu m minimum gate lengths must be used in a conventional MESFET process to avoid deleterious short-channel effects.<<ETX>>

A GaAs MESFET voltage reference

A precision temperature-insensitive voltage reference technique for use in monolithic GaAs A/D (digital/analog) and D/A (digital/analog) converter subsystems has been developed. The principle of operation is the summation of two temperature-dependent drain current terms of equal magnitudes but opposite signs. A negative dI/dT term is obtained from one GaAs MESFET operated in the square-law region, while a positive dI/dT term comes from a second MESFET operated in the subthreshold saturation region. By summing these currents into an on-chip temperature-insensitive NiCr resistor, a reference voltage with a temperature coefficient of only 65 p.p.m./ degrees C over a 200 degrees C temperature range is obtained. The circuit has been implemented in a 0.25- mu m buried-channel recessed-gate depletion-mode GaAs technology.<<ETX>>