Hsin-Shu Chen

11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS

Analog-to-digital converters (ADC) are extensively used in wireless sensor networks and healthcare electronic devices to monitor long-term signal conditions. It is essential to prolong battery life in these applications by using an energy-efficient ADC. A successive-approximation register (SAR) architecture, mostly composed of digital circuits, can achieve low power under low supply voltages [1,2]. Power consumption can be decreased by using either an energy-efficient capacitive-DAC switching method [1] or a low-power comparator with a majority voting technique [2]. In this work, a small coarse ADC resolves the MSB bits. Then, a detect-and-skip algorithm and an aligned switching technique are used to reduce the big fine DAC switching energy. The comparator power is also decreased by utilizing a low-power comparator during coarse conversion and a low-noise comparator during fine conversion. As a result, its FoM performance is as low as 0.85fJ/conversion-step, which is about 3 times better than that of the state-of-the-art work [2].

A 14-b 20-Msamples/s CMOS pipelined ADC

The performance of high-resolution pipelined ADCs is limited by the residue amplifier gain and settling accuracy. In typical implementations, error sources are capacitor ratio mismatch, op-amp gain, and residue settling. All these affect ADC performance adversely, specifically in high-speed ADCs. Capacitor matching improves as capacitor size increases, but the trend is towards shrinking capacitor size for high-speed conversion. Many innovations to overcome this such as ratio-independent techniques are reported. Among them, capacitor error-averaging offers an advantage of achieving both INL and DNL improvements over that achievable by capacitor matching, but it requires three clock phases-one extra clock phase for averaging capacitor errors. In this work, the one extra clock phase is used advantageously for comparison.

A High-Efficiency CMOS DC-DC Converter With 9-

This paper presents an efficient CMOS dc-dc converter with fast transient recovery. A fast-transient control operating in conjunction with a linearly scaled gate-driving technique is used to concurrently improve the transient response and light-load efficiency of a dc-dc converter. The controller operates under a pulse-width modulation mode during steady state and enables a saturation mode during transient to attain fast transient response. The linearly scaled gate-driving technique optimizes the gate-driving voltage with respect to the changing load leading to lower gate-driving loss and better light-load efficiency. A prototype chip was implemented using a commercial 0.35-μm CMOS process to validate the proposed techniques. The measurement result shows a 5% increase in light-load efficiency and achieves an overall maximum efficiency of 90%. Moreover, the transient recovery time of a 450 mA step load change is less than 9 μs.

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A 10-b 320-MS/s pipeline analog-to-digital converter (ADC) with low dc gain opamps, as low as 30.6 dB based on simulations, in its multiplying digital-to-analog converters (MDACs) is presented. A foreground self-calibration technique is proposed to reduce stage gain error by adjusting feedback factor with a calibration capacitor array. The prototype in 90-nm low-power CMOS technology achieves conversion rate of 320 MS/s with peak SFDR and SNDR of 66.7 and 54.2 dB, respectively. The total power dissipation is 42 mW, and it occupies an active chip area of 0.21 mm2 including the calibration circuit. It results in a figure-of-merit (FOM) of 442 fJ/conversion-step. Only 168 clock cycles are used, and no external precise reference sources are needed for the calibration.

s Transient Recovery Time

Under the platform of a high-speed double-data-rate three (DDR3) memory module, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity (SI/PI). For SI part, accurate modeling strategies for signal channels are verified by experiments on samples of address lines. The following what-if analyses of eye diagrams help to identify the discontinuities of package trace to be the bottlenecks and have great effects on the eye diagrams. For PI issues, the modeling methodologies for power distribution networks of data buses are demonstrated and validated with the results of measurement. The analysis indicates that the parasitic effects of the low-cost package structure are the most critical, depicting the importance of improved package design in the next-generation DDR memory modules.

A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC

An integrated 1-V, 50-GHz CMOS voltage-controlled-oscillator (VCO) is presented for the emerging 60-GHz UWB applications. Implemented in a commercial 0.18/spl mu/m CMOS technology, the core VCO circuitry consumes 4mW of power and occupies only 90/spl mu/m/spl times/120/spl mu/m of the silicon estate. The high quality-factor line inductors and NMOS varactors are used to construct the LC-resonators. The measured phase noise at 1-MHz offset from 49 GHz is -96 dBc/Hz, which leads to an excellent figure-of-merit (FOM) of -184 dBc/Hz.

Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis

A low-voltage energy-efficient SAR ADC is presented in this paper with four techniques. Arbitrary weight capacitor array tolerates errors to reduce conversion time. To operate under low voltage, DAC common mode level shift and leakage reduction sample switch with a charge pump are proposed. Differential control logic is used to save its digital power. The prototype ADC consumes 170nW at 100KS/s from a 0.35V supply. It achieves an SNDR of 56.3dB at Nyquist rate and its FOM is 3.2fJ/c.-s.

A 1-V CMOS VCO for 60-GHz applications

This paper presents a successive approximation analog-to-digital converter (SAR ADC) achieving high power efficiency by adopting sub-range concept. Overlapping range greatly relieves the accuracy requirement on the first 6 bit resolving in coarse conversion. The error made in the coarse conversion is recovered during the rest 7 bit resolving in fine conversion. Hence, it significantly reduces the capacitor array output settling time of most-significant-bit (MSB) capacitor switching, which is the speed bottleneck for traditional SAR ADC. A 3mW 12b 10MS/s sub-range SAR ADC is realized in 0.13-μm CMOS process. The prototype circuit reaches SNDR 59.7dB at Nyquist input frequency. It occupies an active chip area of 0.096 mm2.

A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS

This paper presents an inductor current average control (ICAC) method that minimizes the undesirable transient glitches in dc-dc converters using a frequency-hopping pulsewidth modulation control. The analysis in this paper shows that without careful control of the frequency-hopping instant for the dc-dc converters, the transient glitches can be rather large in magnitude and may interfere with the modulated signal to be transmitted from a mobile communication device. The ICAC technique selects the frequency-hopping instant such that the average inductor current is undisturbed when the switching frequency hops. The measurement result shows that the ICAC technique can suppress the transient spurs by 14.1 dB and the voltage of the transient glitches by 65.3%.

A 3mW 12b 10MS/s sub-range SAR ADC

This brief presents a single-channel two-step successive approximation register (SAR) analog-to-digital converter (ADC) using a source follower as an interstage residue amplifier. An asynchronous SAR ADC with two-step timing can effectively allocate the bit-resolving procedure into the whole clock period and eliminate a dedicated duty-cycle clock generator. The arbitrary weight capacitor array technique is utilized to tolerate offset mismatch between the coarse and fine stages. The level-shift technique is used to accelerate the comparator. The ADC in 40-nm CMOS obtains 5.6 and 4.9 effective numbers of bits at Nyquist with the conversion rate of 800 MS/s and 1 GS/s, respectively. It consumes 5.3 mW at 1 GS/s and achieves a figure of merit of 180 fJ/ conversion-step. The core circuit occupies an area of 0.009 mm2.