Hsueh-Chung Chen

Resistance Increase in Metal Nano-wires

As the dimension of copper interconnect scales into the nano-meter regime, the resistivity of copper rapidly increases, primarily due to an electron scattering effect and other dimensional dependent factors, such as film quality. In this paper, we attempt to use a simplified parameter, dimension impact factor (DIF), which includes both surface and grain boundary scattering, to characterize the dimensional dependency of metal resistivity. Among the metal studied, silver has the largest DIF while aluminum has the lowest value. The chief reason is that aluminum has a short electron mean free path (MFP), meaning that it tends to be less affected by dimensional scaling, and has a higher electron specular ratio. In addition to the factor of MFP, resistivity can be affected by other dimensional dependent factors, such as film quality

Low capacitance approaches for 22nm generation Cu interconnect

Various integration approaches, including homogeneous porous Low-k and air gaps, for low-capacitance solution were investigated for 22nm Cu interconnect technology and beyond. For homogeneous Low-k approach, K=2.0 Low-k material is successfully integrated with Cu. Up to 15% line to line capacitance reduction compared with LK-1 (K= 2.5) was demonstrated by a damage-less etching and CMP process. For air gap approach, a cost-effective and Selective air gaps formation process was developed. Air gaps are selectively formed only at narrow spacing between conduction lines without additional processes.

A flexible top metal structure to improve ultra low-k reliability

High stresses generated from chip-package interactions (CPI), especially when large die is flip mounted on organic substrate using Pb-free C4 bumps, can easily cause low-k delamination. A novel scheme by applying an elastic material can effectively reduce the transmitted stresses and, thus, resolve the interfacial delamination issue. Along with an optimized chip-package integration solution, a reliable interconnect structure with good electrical performance, has been successfully demonstrated.

Challenges of Low Effective-K approaches for future Cu interconnect

Challenges of various Low Effective-K approaches, including homogeneous Low-K and Air-Gap, for next generation Cu/Low-K interconnect will be presented. For homogeneous Low-K approach, top issues and possible solutions for K damage, package, and CMP peeling & plannarization due to introduction of fragile lower k (K≪2.4) insulator will be focused. For Air-Gap, various types of Air-Gaps will be reviewed from the points of cost, layout/designer, and new processes involved.