Qiuxia Xu

A specular spin valve with discontinuous nano-oxide layers

Microstructures of the specular spin valve with two nano-oxide layers (NOL1 and NOL2) have been studied at the atomic level. When the NOLs are incorporated in a bottom-pinned spin valve, a significant enhancement in magnetoresistance ratio with greatly decreased sense-layer thickness is achieved. Cross-sectional high-resolution electron microscopy (HREM) studies show that the NOL1 introduced from oxidation of the original bottom-pinned CoFe layer is actually a mixture of oxides and ferromagnetic metals. No CoFe oxides but Ta2O5 is found over the oxidation-treated CoFe sense layer by HREM and x-ray photoelectron spectroscopy study. The Ta2O5 layer acting as the NOL2 can be interpreted as being formed through a solid-state oxidation reaction between the oxidized CoFe sense layer and the Ta capping layers.

Study on characteristics of thermally stable HfLaON gate dielectric with TaN metal gate

We have fabricated the thinnest equivalent oxide thickness of 0.62 nm HfLaON gate dielectric for TaN/HfLaON/SiOx gate stack with improved thermal stability and electrical characteristics. The HfLaON film was deposited using reactive sputtering of Hf–La and Hf targets by alternate means in N2/Ar ambience. The effects of different postdeposition annealing conditions and various La contents on the properties of HfLaON film and its interface have been investigated; the corresponding mechanisms are discussed. The gate tunneling leakage is five orders of magnitude lower than the normal polycrystalline silicon/SiO2 structure. The effective work function with TaN metal gate is 4.06 eV.

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.

Characterization of 1.9- and 1.4-nm ultrathin gate oxynitride by oxidation of nitrogen-implanted silicon substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.

High-Performance Silicon Nanowire Gate-All-Around nMOSFETs Fabricated on Bulk Substrate Using CMOS-Compatible Process

In this letter, a novel self-aligned CMOS-compatible method for the fabrication of gate-all-around silicon nanowire MOSFETs (GAA SNWFETs) on bulk substrate has been proposed. The fabricated SNWFET featuring 33-nm gate length and 7-nm diameter shows the highest driving current (<i>I</i>_on = 2500 μA/μm at <i>V</i>_ds = <i>V</i>_gs = 1.0 V) among previously reported data and achieves high <i>I</i>_on/<i>I</i>_off ratio of 10⁵, lightening the promise for high performance and strong scalability of GAA SNWFETs. The process details and optimization procedure are extensively discussed.

Performance Breakthrough in Gate-All-Around Nanowire n- and p-Type MOSFETs Fabricated on Bulk Silicon Substrate

We demonstrate high-performance silicon-nanowire gate-all-around MOSFETs (GAA SNWFETs) fabricated on bulk Si by a novel top-down complementary MOS-compatible method. The fabricated nand p-type GAA SNWFETs of ~50-nm gate length and of ~6-nm diameter show superior device performance, i.e., driving capability of 2.6 × 10³/2.9 × 10³ μA/μm at |V_D| = |V_G - V_t| = 1.0 V, I_on/I_off ratio as high as 5 × 10⁸/10⁹, and excellent short-channel-effect immunity with subthreshold slope of 67/64 mV/dec and drain-induced barrier lowering of 6 mV/V, respectively. GAA SNWFETs and FinFETs fabricated on bulk Si were also compared by the investigation of both experiments and Technology Computer Aided Design simulation. The superiority of GAA SNWFETs over FinFETs is evidenced in this paper.

The investigation of key technologies for sub-0.1-/spl mu/m CMOS device fabrication

The fabrication of sub-0.1-/spl mu/m CMOS devices and ring oscillator circuits has been successfully explored. The key technologies include: lateral local super-steep-retrograde (SSR) channel doping with heavy ion implantation, 40-nm ultrashallow source/drain (S/D) extension, 3-nm nitrided gate oxide, dual p/sup +//n/sup +/ poly-Si gate electrode, double sidewall scheme, e-beam lithography and RIE etching for sub-0.1-/spl mu/m poly-Si gate pattern, thin and low sheet resistance SALICIDE process, etc. By these innovations in the technologies, high-performance sub-0.1-/spl mu/m CMOS devices with excellent short-channel effects (SCEs) and good driving ability have been fabricated successfully; the shortest channel length is 70 nm. 57 stage unloaded 0.1-/spl mu/m CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V, respectively, are achieved.

High carrier mobility in suspended-channel graphene field effect transistors

A channel suspension method to fabricate high performance graphene field effect transistors (GFET) is presented in this paper. The balance is reached between gate efficiency and carrier mobility. A GFET with 15 μm × 15 μm gate dimension achieves a high normalized transconductance. Peak intrinsic carrier mobility is extracted to be 44 600 cm2v−1s−1. Suspension of the graphene channel is confirmed by AFM, SEM, and gate capacitance measurements. Unlike traditional substrate supported GFET, the proposed suspended-channel structure suppresses the influence of extrinsic scatterings and, meanwhile, maintains a certain gate controllability.

Hole mobility enhancement of pMOSFETs with strain channel induced by Ge pre-amorphization implantation for source/drain extension

A simple, highly manufacturable process has been demonstrated to induce a uniaxial compressive stress in the channel to gain enhanced pMOSFETs performance without additional mask. By integrating Ge pre-amorphization implantation (PAI) for S/D extension of pMOS device, up to 32% hole effective mobility improvement has been obtained comparing control one at 0.6 MV/cm vertical field, and the hole mobility enhancement is nearly kept at higher vertical field. The scaling of feature size, such as gate length and channel width, strengthen the enhancement of the hole effective mobility greatly. The electron effective mobility has a negligible affection.

Low-Cost and Highly Manufacturable Strained-Si Channel Technique for Strong Hole Mobility Enhancement on 35-nm Gate Length pMOSFETs

Local strained-silicon channel pMOSFETs with minimum gate length down to 22 nm have been fabricated by integrating Ge preamorphization implantation (PAI) for source/drain (S/D) extension, which induces a uniaxial compressive stress in the channel to attain an enhanced pMOSFET performance without additional masks. A 43 % improvement of hole effective mobility has been obtained for 35-nm gate length pMOSFETs with an optimized Ge PAI condition for S/D extension at 1.1-MV cm vertical effective field, and the hole mobility improvement is nearly maintained at higher vertical field. The corresponding enhancement of a saturated drive current is 25 % at 1.3-MV ldr cm vertical field. The scaling strengthens the enhancement of the hole mobility remarkably. No negative effect on electron effective mobility is observed. An analysis by using a zero-order Laue zone diffraction on large angle convergent beam electron diffraction patterns in a transmission electron microscopy confirms that the significant residual compressive strain up to -3.0 % in the channel region is induced for 60-nm gate length strained channel pMOSFETs with the same optimized Ge PAI condition as that of 35-nm gate length pMOSFETs. The depth profiles of the residual compressive strain and shear strain in the channel region are given, respectively. The possible mechanisms are discussed.