Hubert Enichlmair

Interface traps density-of-states as a vital component for hot-carrier degradation modeling

We refine our approach for hot-carrier degradation modeling based on a thorough evaluation of the carrier energy distribution by means of a full-band Monte–Carlo simulator. The model is extended to describe the linear current degradation over a wide range of operation conditions. For this purpose we employ two types of interface states, either created by single- or by multiple-electron processes. These traps apparently have different densities of states which is important to consider when calculating the charges stored in these traps. By calibrating the model to represent the degradation of the transfer characteristics, we extract the number of particles trapped by both types of interface traps. We find that traps created by the single- and multiple-electron mechanisms are differently distributed over energy with the latter shifted toward higher energies. This concept allows for an accurate representation of the degradation of the transistor transfer characteristics.

Secondary generated holes as a crucial component for modeling of HC degradation in high-voltage n-MOSFET

We propose a physics-based model for hot-carrier degradation (HCD), which is able to represent HCD observed in n-channel high-voltage MOSFETs with different channel length with a single set of physical parameters. Our approach considers not only damage produced by channel electrons but also by secondary generated channel holes. Although the contribution of the holes to the total defect creation is smaller compared to that of electrons, their impact on the linear drain current is comparable with the electronic one. The reason behind this trend is that hole-induced traps are shifted towards the source, thereby more severely affecting the device behavior.

Hot-carrier degradation modeling using full-band Monte-Carlo simulations

We propose and verify a model for hot carrier degradation based on the exhaustive evaluation of the energy distribution function for charge carriers in the channel by means of a full-band Monte-Carlo device simulator. This approach allows us to capture the interplay between “hot” and “colder” electrons and their contribution to the damage build-up. In fact, particles characterized by higher energy are able to produce interface traps by a single-carrier process while colder ones trigger multivibrational mode excitation of a Si-H bond. For the model validation we use long-channel MOSFETs and represent the degradation of the linear drain current. The single-carrier component dominates degradation (this is the usual tendency for long devices), however, the multiple-carrier process is still considerable being less and less pronounced as the source-drain stress voltage increases

Physics-Based Hot-Carrier Degradation Modeling

We present a thorough analysis of physics-based hot-carrier degradation (HCD) models. We discuss the main features of HCD such as its strong localization at the drain side of the device, the weakening of the degradation at higher temperatures, and the change of the worst-case condition in small devices. The first feature is related to “hot” carriers, while the second is controlled by the fraction of “colder” particles. The latter feature is related to the change of the silicon-hydrogen bondbreakage mechanism from the singleto multiple-carrier process. All these findings suggest that the interface state creation process is controlled by the manner how the carriers are distributed over energy, that is, by the carrier energy distribution function. We distinguish between three main aspects of the physical picture behind hot-carrier degradation: carrier transport, microscopic mechanisms of defect creation and simulation of degraded devices. Therefore, we analyze and classify the existing HCD models in this context. Finally we present our hot-carrier degradation model based on a thorough evaluation of this distribution function by means of a full-band Monte-Carlo device simulator. Our approach tries to address the whole hierarchy of physical phenomena in order to capture all the essential aspects of hot-carrier

TCAD Modeling of Negative Bias Temperature Instability

At elevated temperatures, pMOS transistors show a considerable drift in fundamental device parameters such as the threshold voltage when a large negative bias is applied. This phenomenon, known as negative bias temperature instability, is regarded as one of the most important reliability concerns in highly scaled pMOS transistors. Modeling efforts date back to the reaction-diffusion (RD) model proposed by Jeppson and Svensson forty years ago which has been continuously refined since then. So far, the change in the interface state density predicted by the RD model is directly used to approximate the threshold voltage shift. Here we present a coupling of the RD model to the semiconductor equations which is required to go beyond that approximation and to study degradation during realistic device operating conditions. It is also shown that such a coupled treatment is required to accurately model the behavior during the measurement phase. In addition, the RD model is extended to improve the prediction both in the stress and the relaxation phase by accounting for trap-controlled transport of the released hydrogen species

Impact of the carrier distribution function on hot-carrier degradation modeling

We employ a physics-based model for hot-carrier degradation (HCD), which includes three main sub-tasks: the carrier transport module, a module describing interface state generation and a module for the simulation of the degraded devices. We examine different realizations of the model: with the transport module represented by Monte-Carlo, energy transport and drift-diffusion schemes. The main version, based on the Monte-Carlo approach, is able to represent HCD observed in different MOSFETs using the same set of the model parameters. These parameters have reliable and physically reasonable values. Therefore, we check whether two other versions are capable of the same representation (with the same parameters) or not. It appears that the simplified treatments fail to describe the degradation in devices of the same architecture but with different channel lengths employing a unique set of parameters. This circumstance suggests that a comprehensive HCD model has to be based on a rigorous solution of the Boltzmann transport equation (e.g. by means of a Monte-Carlo method).

Modeling of Hot-Carrier Degradation in nLDMOS Devices: Different Approaches to the Solution of the Boltzmann Transport Equation

We propose two different approaches to describe carrier transport in n-laterally diffused MOS (nLDMOS) transistor and use the calculated carrier energy distribution as an input for our physical hot-carrier degradation (HCD) model. The first version relies on the solution of the Boltzmann transport equation using the spherical harmonics expansion method, while the second uses the simpler drift-diffusion (DD) scheme. We compare these two versions of our model and show that both approaches can capture HCD. We, therefore, conclude that in the case of nLDMOS devices, the DD-based variant of the model provides good accuracy and at the same time is computationally less expensive. This makes the DD-based version attractive for predictive HCD simulations of LDMOS transistors.

Analysis of the threshold voltage turn-around effect in high-voltage n-MOSFETs due to hot-carrier stress

The turn-around effect of the threshold voltage shift during hot-carrier stress has been investigated. Such a phenomenon is explained by the interplay between interface states and oxide traps, i.e. by the compensation of the rapidly created oxide charges by the more slowly created interface states. To prove this idea, a refined extraction scheme for the defect distribution from charge-pumping measurements has been employed. The obtained results are in a good agreement with the findings of our physics-based model of hot-carrier degradation. This approach considers not only damage produced by channel electrons but also by secondary generated channel holes. Although the contribution of the holes to the total defect creation is smaller compared to that of electrons, their impact on the threshold voltage shift is comparable with the electronic contribution. The reason behind this trend is that hole-induced traps are shifted towards the source, thereby more severely affecting the device behavior.

Hot carrier stress degradation modes in p-type high voltage LDMOS transistors

The hot carrier stress induced device degradation of a p-type LDMOS high voltage transistor is investigated at different stress conditions. The influence of shallow trench corner rounding and carbon ion implantation into the shallow trench region is discussed. Numerical device simulations, charge pumping measurements and electrical characterisations are used for these investigations.

Negative bias temperature instability modeling for high-voltage oxides at different stress temperatures

The temperature bias instability of high-voltage oxides is analyzed. For the investigation of negative bias temperature instability (NBTI) we present an enhanced reaction–diffusion model including trap-controlled transport, the amphoteric nature of the Pb centers at the Si/SiO2 interface, Fermi-level dependent interface charges, and fully self-consistent coupling to the semiconductor device equations. Comparison to measurement data for a stress/relaxation cycle and a wide range of temperatures shows excellent agreement. 2007 Elsevier Ltd. All rights reserved.