Hugo Serra

A switched-capacitor biquad using a simple quasi-unity gain amplifier

This paper presents a SC biquad using a simple quasi-unity gain amplifier. In sub-nanometer CMOS technologies the intrinsic gain of the transistors is low, this increases the difficulty of designing high gain amplifiers. The proposed SC filter is based on the Sallen-Key biquad and it requires only a simple low gain amplifier. A differential filter circuit, including a suitable low gain amplifier based on a fully-differential voltage-combiner is presented. The correct functionality of this circuit is validated through electrical simulations of a cascaded sixth order filter. These simulations show that for a clock frequency of 100 MHz, the frequency response of the circuit is very similar to the one of the prototype filter, with only a relative error of 1.1% in the attenuation value at the cutoff frequency.

Analysis of a Multi-Ratio Switched Capacitor DC-DC Converter for a Supercapacitor Power Supply

An energy harvesting system can use a supercapacitor in order to store energy; however, a voltage regulator is required to obtain a constant output voltage as the supercapacitor discharges. A Switched-Capacitor DC-DC converter allows for complete integration in CMOS technology, but requires several topologies in order to obtain a high efficiency. This paper presents the complete analysis of these topologies in order to determine expressions that allow to design and determine the optimum input voltage ranges for each topology. These expressions are verified using electrical simulations.

A top-down optimization methodology for SC filter circuit design

The manual design of Switched-Capacitor (SC) filters can be a laborious process. When these filters use low gain amplifiers or voltage followers instead of high gain opamps, this task becomes even more complex due to the loss of the virtual ground node, requiring the compensation of the parasitic capacitances during the design phase. This paper proposes an automatic procedure for the design of SC filters using low gain amplifiers, including the automatic compensation of the parasitic capacitances. This design methodology is based on a Genetic Algorithm (GA) using hybrid cost functions. The cost function first uses equations to estimate the filter transfer function, the gain and settling-time of the amplifier and the RC time constants of the switches. This reduces the computation time, thus allowing to use large populations to cover the entire design space. Once all specifications are met, the GA uses transient electrical simulations of the circuit in the cost functions, thus resulting in a high accuracy in the determination of the filters transfer function and allowing to accurately compensate the parasitic capacitances and obtain the final design solution within a reasonable computation time.

Automatic design of high-order SC filter circuits

The manual design of Switched-Capacitor (SC) filters can be a strenuous process. This task becomes even more complex when the high gain amplifier is replaced by a low gain amplifier due to the loss of the virtual ground node, increasing the complexity of the filters transfer function and requiring the compensation of the parasitic capacitances during the design phase. This paper proposes an automatic procedure for the design of high order SC filters using low gain amplifiers. The design methodology is based on a Genetic Algorithm (GA) using hybrid cost functions with varying goal specifications. The cost function first uses equations for the estimation of the filters transfer function and, once the specifications are met, the filter is further optimized in order to increase its robustness to random variations. Afterwards, the gain and settling time of the amplifier is also estimated using equations and optimized against several process corners. The use of equation-based cost functions reduces the computation time, allowing the use of larger populations to cover the entire design space. Once all specifications are met, the GA uses transient electrical simulations of the circuit in the cost functions, resulting in the accurate determination of the filters transfer function, and obtaining the final design solution within a reasonable amount of computation time.

A Top-Down Optimization Methodology for SC Filter Circuit Design Using Varying Goal Specifications

The design of Switched-Capacitor (SC) filters can be an arduous process, which becomes even more complex when the high gain amplifier is replaced by a low gain amplifier or a voltage follower. This eliminates the virtual ground node, requiring the compensation of the parasitic capacitances during the design phase. This paper proposes an automatic procedure for the design of SC filters using low gain amplifiers, based on a Genetic Algorithm (GA) using hybrid cost functions with varying goal specifications. The cost function first uses equations to estimate the filter transfer function, the gain and settling-time of the amplifier and the RC time constants of the switches. This reduces the computation time, thus allowing the use of large populations to cover the entire design space. Once all specifications are met, the GA uses transient electrical simulations of the circuit in the cost functions, resulting in the accurate determination of the filter’s transfer function and allowing the accurate compensation of the parasitic capacitances, obtaining the final design solution within a reasonable computation time.

A Switched-Capacitor Band-Pass Biquad Filter Using a Simple Quasi-unity Gain Amplifier

This paper presents a switched-capacitor (SC) band-pass biquad using a simple quasi-unity gain amplifier. In sub-nanometer CMOS technologies the intrinsic gain of the transistors is low; this increases the difficulty of designing high gain amplifiers. The proposed SC filter is based on the Sallen-Key biquad and it requires only a simple low gain amplifier. A differential filter circuit, including a suitable amplifier based on a fully-differential voltage-combiner is presented and analyzed. The correct functionality of this circuit is validated through electrical simulations of a second-order band-pass filter. These simulations show that, for a clock frequency of 100 MHz, the frequency response of the circuit is similar to the corresponding prototype filter.

A 50 Hz SC notch filter for IoT applications

This paper presents a SC 50 Hz notch filter for an analog to digital acquisition channel in an IoT water management sensor node. The notch filter is used to attenuate the unwanted 50 Hz interference, allowing to reduce the required effective resolution of the ADC, which is a ΣΔ modulator with a sampling frequency of 2 MHz. Due to the large ratio between the sampling frequency and the pole frequency, which increases the capacitor values dispersion, charge division branches are used to allow the delivery of a small charge using a larger capacitor, reducing the capacitor spread. The factor by which the value of the capacitors can be increased is controlled by the number of set/reset cycles that are used in the charge division branches. The maximum number of cycles is dependent on the time constants of each node and the gain value of the amplifiers. The notch filter has a total power dissipation below 300 μW and electrical simulations show an attenuation of approximately 30 dB in the unwanted 50 Hz signal.

A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC

In this work, a new two-step radio receiver architecture is proposed, fully embedding two downconversion stages into a charge-sharing (CS) SAR ADC. In order to relax the sampling rate requirements of the ADC, the input signal is firstly downconverted into a specific IF prior to quantization, by a 4-Tap time-interleaved FIR filter in a subsampling manner. Since the ADC can embed the downconversion operation, a smaller subsampling ratio can be used, thus reducing the out-of-band noise density at the output and improving performance. Circuit-level simulations demonstrate, through an 8-bit CS SAR ADC, a SNDR of 48.2 dB, THD of −56.6 dB and a SFDR of 55.1 dB, in a structure that entirely renounce conventional mixer stages. As a consequence, significant power and area savings are expected, together with improved noise and linearity performances.

Switched-Capacitor Circuits

This chapter introduces SC circuits. A brief description is given for the main building blocks of a SC filter (operational amplifiers, switches, capacitors, and non-overlapping clock phases). A few examples of SC resistor emulation circuits are presented along with their equivalent resistance. Two examples of SC integrators are also shown, one with the resistors implemented with a T branch (parasitic-sensitive integrator) and another with a branch in π (parasitic-insensitive integrator). A signal flow graph is presented which allows large circuits to be analyzed graphically. The chapter ends with the two Sallen-Key topologies designed in this book, in their continuous time version.

Low-Pass Filter Topologies

Low-pass filters are systems that allow the passing without attenuation of signals with frequency below the cutoff frequency, while attenuating those with frequency above it. The amount of attenuation the signals with higher frequency suffer is dependent on their frequency and the order of the filter. In this chapter low-pass SC filters based on the continuous-time version of the Sallen-Key low-pass filter [8] will be presented and discussed when using ideal components. Higher order low-pass SC filters using cascaded sections will also be discussed in this chapter.