Rui Santos-Tavares

A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 μm 1.2 V standard CMOS technology are shown.

Two-stage fully-differential inverter-based self-biased CMOS amplifier with high efficiency

This paper describes a novel two-stage fully-differential CMOS amplifier comprising two self-biased inverter stages, with optimum compensation and high efficiency. Although it relies on a class A topology, it is shown through simulations, that it achieves the highest efficiency of its class and comparable to the best class AB amplifiers. Due to the self-biasing, a low variability in the DC gain over process, temperature, and supply is achieved. A detailed circuit analysis, a design methodology for optimization and the most relevant simulation results are presented, together with a final comparison among state-of-the-art amplifiers.

Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners

This paper presents the design of single-stage amplifiers with enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward techniques. Instead, two voltage-combiners are used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of a properly optimized circuit example, using AIDA-C a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that DC gains above 50 dB can be achieved, together with high energy efficiency (a figure-of-merit of about 1300 MHz-pF/mA has been achieved).

Optimization of multi-stage amplifiers in deep-submicron CMOS using a distributed/parallel genetic algorithm

This paper presents a framework for time-domain optimization of amplifiers employing a parallel genetic algorithm based on a message passing interface. This methodology achieves a considerable reduction in the optimization time (up to 19 times faster than a serial implementation). Increasing the processing capacity allows searching within a larger design space using complex transistors models, yielding more accurate results. The optimization, based on transient simulations, is possible due to the integration of a genetic algorithm optimizer together with the open-source simulator NGSPICE source-code.

Optimum Sizing and Compensation of Two-Stage CMOS Amplifiers Based On a Time-Domain Approach

This paper presents a new design methodology for optimum sizing and compensation of two-stage amplifiers based on a time-domain approach. This methodology allows the analysis of different topologies of amplifiers with an unlimited number of poles and zeros. The optimization process is performed by a software tool based on a genetic algorithm kernel integrated with open-source BSIM3v3 code. Using this tool together with the proposed design flow it is demonstrated, with consistent simulated results, that the optimum step-response is achieved using hybrid cascode-compensation comprising two un-equal sized capacitors.

A top-down optimization methodology for SC filter circuit design

The manual design of Switched-Capacitor (SC) filters can be a laborious process. When these filters use low gain amplifiers or voltage followers instead of high gain opamps, this task becomes even more complex due to the loss of the virtual ground node, requiring the compensation of the parasitic capacitances during the design phase. This paper proposes an automatic procedure for the design of SC filters using low gain amplifiers, including the automatic compensation of the parasitic capacitances. This design methodology is based on a Genetic Algorithm (GA) using hybrid cost functions. The cost function first uses equations to estimate the filter transfer function, the gain and settling-time of the amplifier and the RC time constants of the switches. This reduces the computation time, thus allowing to use large populations to cover the entire design space. Once all specifications are met, the GA uses transient electrical simulations of the circuit in the cost functions, thus resulting in a high accuracy in the determination of the filters transfer function and allowing to accurately compensate the parasitic capacitances and obtain the final design solution within a reasonable computation time.

A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner

This paper presents the design and the electrical simulations of a single-stage amplifier with high energy-efficiency and enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward techniques. Instead, a fully-differential folded voltage-combiner block is used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of the properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that a DC gain above 50 dB can be achieved, together with high energy efficiency. A simulated figure-of-merit above 2200 MHz×pF/mA has been reached. The circuit was designed using a 130 nm CMOS technology, draining approximately 0.2 mA from a 1.2 V power supply.

The design of an audio power amplifier as a class project for undergraduate students

This paper presents the design of an audio power amplifier as a class project for undergraduate students of electrical engineering. This project is part of an electronics introduction class for undergraduate students and it has two main objectives: first to teach basic electronic circuit design concepts and second to motivate the students into choosing to learn more about analog circuit design. One of the main reasons for the creation of this project was the realization that most students considered analog design uninteresting. This project allows the students to design and build a circuit that actually has a practical application: at the end of the project the students can use the circuit that they designed to listen to music from an mp3 player through a loudspeaker.

Automatic design of high-order SC filter circuits

The manual design of Switched-Capacitor (SC) filters can be a strenuous process. This task becomes even more complex when the high gain amplifier is replaced by a low gain amplifier due to the loss of the virtual ground node, increasing the complexity of the filters transfer function and requiring the compensation of the parasitic capacitances during the design phase. This paper proposes an automatic procedure for the design of high order SC filters using low gain amplifiers. The design methodology is based on a Genetic Algorithm (GA) using hybrid cost functions with varying goal specifications. The cost function first uses equations for the estimation of the filters transfer function and, once the specifications are met, the filter is further optimized in order to increase its robustness to random variations. Afterwards, the gain and settling time of the amplifier is also estimated using equations and optimized against several process corners. The use of equation-based cost functions reduces the computation time, allowing the use of larger populations to cover the entire design space. Once all specifications are met, the GA uses transient electrical simulations of the circuit in the cost functions, resulting in the accurate determination of the filters transfer function, and obtaining the final design solution within a reasonable amount of computation time.

A Top-Down Optimization Methodology for SC Filter Circuit Design Using Varying Goal Specifications

The design of Switched-Capacitor (SC) filters can be an arduous process, which becomes even more complex when the high gain amplifier is replaced by a low gain amplifier or a voltage follower. This eliminates the virtual ground node, requiring the compensation of the parasitic capacitances during the design phase. This paper proposes an automatic procedure for the design of SC filters using low gain amplifiers, based on a Genetic Algorithm (GA) using hybrid cost functions with varying goal specifications. The cost function first uses equations to estimate the filter transfer function, the gain and settling-time of the amplifier and the RC time constants of the switches. This reduces the computation time, thus allowing the use of large populations to cover the entire design space. Once all specifications are met, the GA uses transient electrical simulations of the circuit in the cost functions, resulting in the accurate determination of the filter’s transfer function and allowing the accurate compensation of the parasitic capacitances, obtaining the final design solution within a reasonable computation time.