Nuno Paulino

An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs

This paper presents an improved low-voltage low-power CMOS comparator suitable for high-speed pipeline ADCs. Simulated results of the proposed circuit in a 0.35 /spl mu/m standard CMOS technology operating at supply voltages within the range of 1.0-1.5 V show that this comparator achieves low offset, reduced kickback noise, high mean-time to failure and exhibits low-power dissipation at very high-speed operation.

Design methodology for optimization of analog building blocks using genetic algorithms

This paper presents an equation-based design methodology for optimization of analog building blocks using genetic algorithms. The proposed methodology uses the analytical equations that describe the circuits behavior as a function of the design parameters such as the transistor dimensions and/or the passive component values. These parameters are then subject to an optimization process, using genetic algorithms, in order to fit the circuit performance into the desired specifications. This design methodology is suited for fast redesigns of analog blocks into new technologies.

A 0.9V /spl Delta//spl Sigma/ Modulator with 80dB SNDR and 83dB DR Using a Single-Phase Technique

A 2nd-order DeltaSigma ADC implemented in 0.18mum CMOS occupies 0.06mm2 and dissipates 0.2mW from a 0.9V supply. It achieves 80dB SNDR and 83dB DR over a 10kHz BW employing a single-phase technique to reach such performance. An amplifier-sharing scheme is proposed to improve power and area efficiency

Design methodology for Sigma-Delta modulators based on a genetic algorithm using hybrid cost functions

The design of Sigma-Delta modulators (ΣΔMs) encompasses different variables that need to be optimized together in order to maximize the performance. The design task is even more complex due to the non-linear behavior of the quantizer. Typically, a linearized model of the quantizer is used to obtain linear equations that predict the performance of the modulator, which may cause significant discrepancies between the predicted and actual behavior of ΣΔMs. To better predict the behavior of a given design solution, we propose a design methodology for ΣΔMs based on a genetic algorithm (GA) that uses both linear equations and simulations: the design solution is evaluated using the equations and, if the performance is good enough, it will be evaluated trough simulation. This hybrid cost function allows to use a GA with a large population and, therefore, obtains the best possible design solution. The hybrid cost function takes thermal noise, quantization noise, voltage swing variations and stability of the modulator into account. Furthermore, it also selects the design solution that is the most insensitive to component variations. The design of a continuous-time (CT) and a discrete-time (DT) ΣΔM are given as proof-of-concept.

A 1.2-V 165-/spl mu/W 0.29-mm 2 Multibit Sigma-Delta ADC for Hearing Aids Using Nonlinear DACs and With Over 91 dB Dynamic-Range

This paper describes the design and experimental evaluation of a multibit Sigma-Delta (ΣΔ) modulator (ΣΔM) with enhanced dynamic range (DR) through the use of nonlinear digital-to-analog converters (DACs) in the feedback paths. This nonlinearity imposes a trade-off between DR and distortion, which is well suited to the intended hearing aid application. The modulator proposed here uses a fully-differential self-biased amplifier and a 4-bit quantizer based on fully dynamic comparators employing MOS parametric pre-amplification to improve both energy and area efficiencies. A test chip was fabricated in a 130 nm digital CMOS technology, which includes the proposed modulator with nonlinear DACs and a modulator with conventional linear DACs, for comparison purposes. The measured results show that the ΣΔM using nonlinear DACs achieves an enhancement of the DR around 8.4 dB (to 91.4 dB). Power dissipation and silicon area are about the same for the two cases. The performance achieved is comparable to that of the best reported multibit ΣΔ ADCs, with the advantage of occupying less silicon area (7.5 times lower area when compared with the most energy efficient ΣΔM).

Low-Power CMOS Comparator with Embedded Amplification for Ultra-high-speed ADCs

In this paper the challenge of improving the energy-efficiency of comparators is addressed, by proposing a novel comparator structure, to be used in ultra-high-speed ADCs. In this comparator, the pre-amplification is embedded in the input switched-capacitor network by using the passive-amplification capability of MOS devices. Simulated results show that this comparator exhibits low-offset ultra-fast regeneration-time and high energy-efficiency.

Novel linearization technique for low-distortion high-swing CMOS switches with improved reliability

This paper proposes a linearization technique for low-distortion high-swing CMOS switches based on a new method of improving the linearity of the NMOS and PMOS conductances. This method has the advantage over conventional clock-boosting techniques of avoiding large gate voltages thus reducing the stress on the gate capacitance. Simulated results of a practical sample-and-hold circuit show that, using this technique, linearity levels compatible with 12-b can be reached over the Nyquist band

Switched-Capacitor Multiply-By-Two Amplifier Insensitive to Component Mismatches

This brief describes a new mismatch-insensitive amplifier with an accurate gain of two and with the parasitic effects compensated. It is based on associating four sets of two capacitors in series during the amplification phase. The amplifier operates within a single clock cycle and uses only one amplifier. A detailed study of the different nonideal effects is presented. Simulated results demonstrate that a gain accuracy enhancement of the order of 4-5 bits can be achieved with respect to conventional realizations

A step-up μ-power converter for solar energy harvesting applications, using Hill Climbing maximum power point tracking

This paper presents a step-up micro-power converter for solar energy harvesting applications. The circuit uses a SC voltage tripler architecture, controlled by an MPPT circuit based on the Hill Climbing algorithm. This circuit was designed in a 0.13 µm CMOS technology in order to work with an a-Si PV cell. The circuit has a local power supply voltage, created using a scaled down SC voltage tripler, controlled by the same MPPT circuit, to make the circuit robust to load and illumination variations. The SC circuits use a combination of PMOS and NMOS transistors to reduce the occupied area. A charge re-use scheme is used to compensate the large parasitic capacitors associated to the MOS transistors. The simulation results show that the circuit can deliver a power of 1266 µW to the load using 1712 µW of power from the PV cell, corresponding to an efficiency as high as 73.91%. The simulations also show that the circuit is capable of starting up with only 19% of the maximum illumination level.

Optimization of multi-stage amplifiers in deep-submicron CMOS using a distributed/parallel genetic algorithm

This paper presents a framework for time-domain optimization of amplifiers employing a parallel genetic algorithm based on a message passing interface. This methodology achieves a considerable reduction in the optimization time (up to 19 times faster than a serial implementation). Increasing the processing capacity allows searching within a larger design space using complex transistors models, yielding more accurate results. The optimization, based on transient simulations, is possible due to the integration of a genetic algorithm optimizer together with the open-source simulator NGSPICE source-code.